Topic: verilator

pulp-platform / ariane

449

Ariane is a 6-stage RISC-V CPU capable of booting Linux

systemverilog-hdl cpu riscv asic fpga rv64gc ariane verilator questasim

SystemVerilog Updated May 1, 2019

ZipCPU / zipcpu

326

A small, light weight, RISC CPU soft core

fpga soft-core cross-compiler verilog verilator wishbone wishbone-bus zipcpu cpu risc-cpu

Verilog Updated Apr 1, 2019

tymonx / logic

75

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

verilog systemverilog hdl systemc uvm cpp cmake modelsim verilator verification rtl unit-tests quartus fpga asic testing-rtl xilinx vivado

SystemVerilog Updated Jul 26, 2018

ZipCPU / autofpga

60

A utility for Composing FPGA designs from Peripherals

wishbone-bus wishbone fpga c-plus-plus verilog verilator

C++ Updated Apr 3, 2019

ZipCPU / openarty

60

An Open Source configuration of the Arty platform

zipcpu fpga fpga-soc arty verilator wishbone-bus wishbone

Verilog Updated Mar 19, 2019

ZipCPU / dblclockfft

50

A configurable C++ generator of pipelined Verilog FFT cores

fft fpga verilog verilator verilog-components gplv3

C++ Updated Nov 26, 2018

ZipCPU / wbuart32

47

A simple, basic, formally verified UART controller

fpga uart uart-verilog verilator wishbone wishbone-bus verilog serialport

Verilog Updated Feb 21, 2019

ZipCPU / vgasim

45

A Video display simulator

verilog video gplv3 fpga gtkmm video-simulator verilator vga

Verilog Updated Dec 7, 2018

ultraembedded / cores

44

Various HDL (Verilog) IP Cores

verilog rtl verilog-hdl fpga verilator verilog-components asic sdram sram audio i2s spi uart usb

Verilog Updated Apr 23, 2019

olofk / edalize

41

An abstraction library for interfacing EDA tools

Python Updated May 3, 2019

ZipCPU / wbscope

28

A wishbone controlled scope for FPGA's

fpga verilog verilator debugging-tools wishbone-bus wishbone

Verilog Updated Nov 19, 2018

ZipCPU / s6soc

24

CMod-S6 SoC

zipcpu fpga fpga-soc verilator wishbone wishbone-bus

Verilog Updated Jan 6, 2018

IBM / hdl-tools

21

Facilitates building open source tools for working with hardware description languages (HDLs)

rtl hdl verilog verilator gtkwave

Perl Updated Jun 24, 2018

ultraembedded / riscv

20

RISC-V CPU Core (RV32IM)

risc-v cpu verilog fpga verilator rv32im rv32i

Verilog Updated Mar 31, 2019

ZipCPU / sdspi

20

SD-Card controller, using a SPI interface that is (optionally) shared

sd-card sd-interface fpga verilog-components verilog verilator wishbone wishbone-bus spi-interface

Verilog Updated Nov 30, 2017

ZipCPU / zbasic

14

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

zipcpu verilator verilog fpga system-on-chip

Verilog Updated Mar 19, 2019

ZipCPU / dpll

12

A collection of phase locked loop (PLL) related projects

verilog pll verilator fpga gplv3

Verilog Updated May 16, 2018

ZipCPU / wbi2c

11

Wishbone controlled I2C controllers

fpga verilator verilog wishbone-bus i2c-master i2c i2c-slave gplv3

C++ Updated May 18, 2018

ZipCPU / interpolation

11

Digital Interpolation Techniques Applied to Digital Signal Processing

dsp interpolation interpolation-methods interpolation-techniques verilog verilator fpga

Verilog Updated May 16, 2018

tymonx / virtio

10

Virtio implementation in SystemVerilog

verilog systemverilog hdl rtl cmake verilator virtio quartus fpga xilinx vivado model systemc

SystemVerilog Updated Jan 23, 2018

AaronKel / Nirah

8

Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable…

verilator python swig verilog system-verilog verification

Verilog Updated Mar 6, 2019

ZipCPU / dbgbus

7

A collection of debugging busses developed and presented at zipcpu.com

fgpa wishbone-bus wishbone debugging-tools verilator verilog

C++ Updated May 11, 2018

poucotm / SublimeLinter-contrib-verilator

5

👌 This linter plugin for SublimeLinter provides an interface to Verilator (Verilog Simulator)

sublime-text sublimelinter verilog verilator linter linter-plugin

Python Updated Feb 8, 2019

ZipCPU / videozip

4

A ZipCPU SoC for the Nexys Video board supporting video functionality

zipcpu hdmi verilator verilog gplv3 soc system-on-chip fpga nexys-video

Verilog Updated Jun 27, 2018

ZipCPU / website

3

The ZipCPU blog

zipcpu zipcpu-blog verilog verilator fpga tutorial learning blog

HTML Updated Apr 28, 2019

ZipCPU / wbicapetwo

3

Wishbone to ICAPE interface conversion

wishbone fpga verilator iprog-command xilinx gplv3

Verilog Updated Sep 21, 2016

kkiningh / rules_verilator

2

A fork of Verilator that includes Bazel build rules

bazel verilog verilator

C++ Updated Dec 23, 2018

msvisser / mMIPS-Verilator

1

Verilator testbench for the mMIPS processor

verilator mips tue

C++ Updated Feb 19, 2018

djg / cpu

1

CPU - Verilog + Rust

cmake rust verilog verilator rtl fpga

CMake Updated Mar 5, 2018

NorthSailor / Feather

1

A single cycle processor implementing a subset of the ARMv7 ISA.

systemverilog verilator digital-design computer-architecture armv7

SystemVerilog Updated Sep 11, 2018

verilator

Repositories 36