Digital logic design tool and simulator
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Updated
Apr 22, 2024 - Java
Digital logic design tool and simulator
Educational software for modelling and simulation of digital circuits.
App that Generate VHDL Code and Testbench template file
Code and data for "On the Naturalness of Hardware Descriptions" in ESEC/FSE'20
VHDL plugin for Intellij
Projects for university
Verification tool for VHDL (or at least the prototype of one).
Eclipse Verilog/VHDL Editor - a fork of the SourceForge repository
Contains all the projects I have done at AUB during my years of studies as a CCE student.
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