Topic: wishbone-bus

ZipCPU / zipcpu

326

A small, light weight, RISC CPU soft core

fpga soft-core cross-compiler verilog verilator wishbone wishbone-bus zipcpu cpu risc-cpu

Verilog Updated Apr 1, 2019

ZipCPU / autofpga

60

A utility for Composing FPGA designs from Peripherals

wishbone-bus wishbone fpga c-plus-plus verilog verilator

C++ Updated Apr 3, 2019

ZipCPU / openarty

60

An Open Source configuration of the Arty platform

zipcpu fpga fpga-soc arty verilator wishbone-bus wishbone

Verilog Updated Mar 19, 2019

ZipCPU / wbuart32

47

A simple, basic, formally verified UART controller

fpga uart uart-verilog verilator wishbone wishbone-bus verilog serialport

Verilog Updated Feb 21, 2019

ZipCPU / wb2axip

35

Bus bridges and other odds and ends

fpga wishbone wishbone-bus axi-bus xilinx xilinx-vivado gplv3

Verilog Updated May 4, 2019

ZipCPU / wbscope

28

A wishbone controlled scope for FPGA's

fpga verilog verilator debugging-tools wishbone-bus wishbone

Verilog Updated Nov 19, 2018

ZipCPU / s6soc

24

CMod-S6 SoC

zipcpu fpga fpga-soc verilator wishbone wishbone-bus

Verilog Updated Jan 6, 2018

ZipCPU / sdspi

20

SD-Card controller, using a SPI interface that is (optionally) shared

sd-card sd-interface fpga verilog-components verilog verilator wishbone wishbone-bus spi-interface

Verilog Updated Nov 30, 2017

lxp32 / lxp32-cpu

14

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

fpga cpu risc soft-core wishbone wishbone-bus risc-cpu risc-processor vhdl

Assembly Updated Feb 25, 2019

ZipCPU / wbi2c

11

Wishbone controlled I2C controllers

fpga verilator verilog wishbone-bus i2c-master i2c i2c-slave gplv3

C++ Updated May 18, 2018

ZipCPU / xulalx25soc

7

A System on a Chip Implementation for the XuLA2-LX25 board

fpga wishbone-bus soc zipcpu

Verilog Updated Dec 13, 2018

ZipCPU / dbgbus

7

A collection of debugging busses developed and presented at zipcpu.com

fgpa wishbone-bus wishbone debugging-tools verilator verilog

C++ Updated May 11, 2018

ZipCPU / wbfmtx

7

A wishbone controlled FM transmitter hack

fm-transmitter fpga wishbone wishbone-bus hack verilog verilog-components

Verilog Updated Sep 21, 2016

semahawk / icarium

1

Trying to implement a soft core SoC

verilog verilog-hdl system-on-chip wishbone wishbone-bus softcore soft-core

Verilog Updated Apr 6, 2019

zz-systems / Plasma-SoC

Plasma MIPS (I) SoC

system-on-chip cpu mips zedboard de1-soc wishbone wishbone-bus

C Updated Sep 17, 2018

pbing / Wishbone

Check Wishbone B4 variants

wishbone wishbone-bus systemverilog

SystemVerilog Updated Aug 30, 2018

semahawk / wishbone

Trying to learn Wishbone by implementing few master/slave devices

wishbone wishbone-bus verilog verilog-hdl

SystemVerilog Updated Jan 7, 2019

pbing / J1_WB

Forth CPU J1 in SystemVerilog and Wishbone interface

systemverilog wishbone-bus wishbone forth-cpu

SystemVerilog Updated Oct 3, 2018

wishbone-bus

Repositories 18