A small, light weight, RISC CPU soft core
Verilog
Updated Apr 1, 2019
A utility for Composing FPGA designs from Peripherals
C++
Updated Apr 3, 2019
An Open Source configuration of the Arty platform
Verilog
Updated Mar 19, 2019
A simple, basic, formally verified UART controller
Verilog
Updated Feb 21, 2019
Bus bridges and other odds and ends
Verilog
Updated May 4, 2019
A wishbone controlled scope for FPGA's
Verilog
Updated Nov 19, 2018
CMod-S6 SoC
Verilog
Updated Jan 6, 2018
SD-Card controller, using a SPI interface that is (optionally) shared
Verilog
Updated Nov 30, 2017
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
Assembly
Updated Feb 25, 2019
Wishbone controlled I2C controllers
C++
Updated May 18, 2018
A System on a Chip Implementation for the XuLA2-LX25 board
Verilog
Updated Dec 13, 2018
A collection of debugging busses developed and presented at zipcpu.com
C++
Updated May 11, 2018
A wishbone controlled FM transmitter hack
Verilog
Updated Sep 21, 2016
Trying to implement a soft core SoC
Verilog
Updated Apr 6, 2019
Plasma MIPS (I) SoC
C
Updated Sep 17, 2018
Check Wishbone B4 variants
SystemVerilog
Updated Aug 30, 2018
Trying to learn Wishbone by implementing few master/slave devices
SystemVerilog
Updated Jan 7, 2019
Forth CPU J1 in SystemVerilog and Wishbone interface
SystemVerilog
Updated Oct 3, 2018