A small, light weight, RISC CPU soft core
Verilog
Updated Apr 1, 2019
An Open Source configuration of the Arty platform
Verilog
Updated Mar 19, 2019
CMod-S6 SoC
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Updated Jan 6, 2018
A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
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Updated Mar 19, 2019
A System on a Chip Implementation for the XuLA2-LX25 board
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Updated Dec 13, 2018
A ZipCPU SoC for the Nexys Video board supporting video functionality
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Updated Jun 27, 2018
The ZipCPU blog
HTML
Updated Apr 28, 2019
A small, light weight, RISC CPU soft core
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