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/*
* advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
*
* Copyright (c) 1995-2000 Advanced System Products, Inc.
* Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
* Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
* Copyright (c) 2014 Hannes Reinecke <hare@suse.de>
* All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
/*
* As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
* changed its name to ConnectCom Solutions, Inc.
* On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
*/
#include <linux/module.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/proc_fs.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/isa.h>
#include <linux/eisa.h>
#include <linux/pci.h>
#include <linux/spinlock.h>
#include <linux/dma-mapping.h>
#include <linux/firmware.h>
#include <linux/dmapool.h>
#include <asm/io.h>
#include <asm/dma.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_device.h>
#include <scsi/scsi_tcq.h>
#include <scsi/scsi.h>
#include <scsi/scsi_host.h>
#define DRV_NAME "advansys"
#define ASC_VERSION "3.5" /* AdvanSys Driver Version */
/* FIXME:
*
* 1. Use scsi_transport_spi
* 2. advansys_info is not safe against multiple simultaneous callers
* 3. Add module_param to override ISA/VLB ioport array
*/
/* Enable driver /proc statistics. */
#define ADVANSYS_STATS
/* Enable driver tracing. */
#undef ADVANSYS_DEBUG
typedef unsigned char uchar;
#define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
#define PCI_VENDOR_ID_ASP 0x10cd
#define PCI_DEVICE_ID_ASP_1200A 0x1100
#define PCI_DEVICE_ID_ASP_ABP940 0x1200
#define PCI_DEVICE_ID_ASP_ABP940U 0x1300
#define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
#define PCI_DEVICE_ID_38C0800_REV1 0x2500
#define PCI_DEVICE_ID_38C1600_REV1 0x2700
#define PortAddr unsigned int /* port address size */
#define inp(port) inb(port)
#define outp(port, byte) outb((byte), (port))
#define inpw(port) inw(port)
#define outpw(port, word) outw((word), (port))
#define ASC_MAX_SG_QUEUE 7
#define ASC_MAX_SG_LIST 255
#define ASC_CS_TYPE unsigned short
#define ASC_IS_ISA (0x0001)
#define ASC_IS_ISAPNP (0x0081)
#define ASC_IS_EISA (0x0002)
#define ASC_IS_PCI (0x0004)
#define ASC_IS_PCI_ULTRA (0x0104)
#define ASC_IS_PCMCIA (0x0008)
#define ASC_IS_MCA (0x0020)
#define ASC_IS_VL (0x0040)
#define ASC_IS_WIDESCSI_16 (0x0100)
#define ASC_IS_WIDESCSI_32 (0x0200)
#define ASC_IS_BIG_ENDIAN (0x8000)
#define ASC_CHIP_MIN_VER_VL (0x01)
#define ASC_CHIP_MAX_VER_VL (0x07)
#define ASC_CHIP_MIN_VER_PCI (0x09)
#define ASC_CHIP_MAX_VER_PCI (0x0F)
#define ASC_CHIP_VER_PCI_BIT (0x08)
#define ASC_CHIP_MIN_VER_ISA (0x11)
#define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
#define ASC_CHIP_MAX_VER_ISA (0x27)
#define ASC_CHIP_VER_ISA_BIT (0x30)
#define ASC_CHIP_VER_ISAPNP_BIT (0x20)
#define ASC_CHIP_VER_ASYN_BUG (0x21)
#define ASC_CHIP_VER_PCI 0x08
#define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
#define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
#define ASC_CHIP_MIN_VER_EISA (0x41)
#define ASC_CHIP_MAX_VER_EISA (0x47)
#define ASC_CHIP_VER_EISA_BIT (0x40)
#define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
#define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
#define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
#define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
#define ASC_SCSI_ID_BITS 3
#define ASC_SCSI_TIX_TYPE uchar
#define ASC_ALL_DEVICE_BIT_SET 0xFF
#define ASC_SCSI_BIT_ID_TYPE uchar
#define ASC_MAX_TID 7
#define ASC_MAX_LUN 7
#define ASC_SCSI_WIDTH_BIT_SET 0xFF
#define ASC_MAX_SENSE_LEN 32
#define ASC_MIN_SENSE_LEN 14
#define ASC_SCSI_RESET_HOLD_TIME_US 60
/*
* Narrow boards only support 12-byte commands, while wide boards
* extend to 16-byte commands.
*/
#define ASC_MAX_CDB_LEN 12
#define ADV_MAX_CDB_LEN 16
#define MS_SDTR_LEN 0x03
#define MS_WDTR_LEN 0x02
#define ASC_SG_LIST_PER_Q 7
#define QS_FREE 0x00
#define QS_READY 0x01
#define QS_DISC1 0x02
#define QS_DISC2 0x04
#define QS_BUSY 0x08
#define QS_ABORTED 0x40
#define QS_DONE 0x80
#define QC_NO_CALLBACK 0x01
#define QC_SG_SWAP_QUEUE 0x02
#define QC_SG_HEAD 0x04
#define QC_DATA_IN 0x08
#define QC_DATA_OUT 0x10
#define QC_URGENT 0x20
#define QC_MSG_OUT 0x40
#define QC_REQ_SENSE 0x80
#define QCSG_SG_XFER_LIST 0x02
#define QCSG_SG_XFER_MORE 0x04
#define QCSG_SG_XFER_END 0x08
#define QD_IN_PROGRESS 0x00
#define QD_NO_ERROR 0x01
#define QD_ABORTED_BY_HOST 0x02
#define QD_WITH_ERROR 0x04
#define QD_INVALID_REQUEST 0x80
#define QD_INVALID_HOST_NUM 0x81
#define QD_INVALID_DEVICE 0x82
#define QD_ERR_INTERNAL 0xFF
#define QHSTA_NO_ERROR 0x00
#define QHSTA_M_SEL_TIMEOUT 0x11
#define QHSTA_M_DATA_OVER_RUN 0x12
#define QHSTA_M_DATA_UNDER_RUN 0x12
#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
#define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
#define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
#define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
#define QHSTA_D_HOST_ABORT_FAILED 0x23
#define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
#define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
#define QHSTA_D_ASPI_NO_BUF_POOL 0x26
#define QHSTA_M_WTM_TIMEOUT 0x41
#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
#define QHSTA_M_TARGET_STATUS_BUSY 0x45
#define QHSTA_M_BAD_TAG_CODE 0x46
#define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
#define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
#define QHSTA_D_LRAM_CMP_ERROR 0x81
#define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
#define ASC_FLAG_SCSIQ_REQ 0x01
#define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
#define ASC_FLAG_BIOS_ASYNC_IO 0x04
#define ASC_FLAG_SRB_LINEAR_ADDR 0x08
#define ASC_FLAG_WIN16 0x10
#define ASC_FLAG_WIN32 0x20
#define ASC_FLAG_ISA_OVER_16MB 0x40
#define ASC_FLAG_DOS_VM_CALLBACK 0x80
#define ASC_TAG_FLAG_EXTRA_BYTES 0x10
#define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
#define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
#define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
#define ASC_SCSIQ_CPY_BEG 4
#define ASC_SCSIQ_SGHD_CPY_BEG 2
#define ASC_SCSIQ_B_FWD 0
#define ASC_SCSIQ_B_BWD 1
#define ASC_SCSIQ_B_STATUS 2
#define ASC_SCSIQ_B_QNO 3
#define ASC_SCSIQ_B_CNTL 4
#define ASC_SCSIQ_B_SG_QUEUE_CNT 5
#define ASC_SCSIQ_D_DATA_ADDR 8
#define ASC_SCSIQ_D_DATA_CNT 12
#define ASC_SCSIQ_B_SENSE_LEN 20
#define ASC_SCSIQ_DONE_INFO_BEG 22
#define ASC_SCSIQ_D_SRBPTR 22
#define ASC_SCSIQ_B_TARGET_IX 26
#define ASC_SCSIQ_B_CDB_LEN 28
#define ASC_SCSIQ_B_TAG_CODE 29
#define ASC_SCSIQ_W_VM_ID 30
#define ASC_SCSIQ_DONE_STATUS 32
#define ASC_SCSIQ_HOST_STATUS 33
#define ASC_SCSIQ_SCSI_STATUS 34
#define ASC_SCSIQ_CDB_BEG 36
#define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
#define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
#define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
#define ASC_SCSIQ_B_SG_WK_QP 49
#define ASC_SCSIQ_B_SG_WK_IX 50
#define ASC_SCSIQ_W_ALT_DC1 52
#define ASC_SCSIQ_B_LIST_CNT 6
#define ASC_SCSIQ_B_CUR_LIST_CNT 7
#define ASC_SGQ_B_SG_CNTL 4
#define ASC_SGQ_B_SG_HEAD_QP 5
#define ASC_SGQ_B_SG_LIST_CNT 6
#define ASC_SGQ_B_SG_CUR_LIST_CNT 7
#define ASC_SGQ_LIST_BEG 8
#define ASC_DEF_SCSI1_QNG 4
#define ASC_MAX_SCSI1_QNG 4
#define ASC_DEF_SCSI2_QNG 16
#define ASC_MAX_SCSI2_QNG 32
#define ASC_TAG_CODE_MASK 0x23
#define ASC_STOP_REQ_RISC_STOP 0x01
#define ASC_STOP_ACK_RISC_STOP 0x03
#define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
#define ASC_STOP_CLEAN_UP_DISC_Q 0x20
#define ASC_STOP_HOST_REQ_RISC_HALT 0x40
#define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
#define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
#define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
#define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
#define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
#define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
#define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
typedef struct asc_scsiq_1 {
uchar status;
uchar q_no;
uchar cntl;
uchar sg_queue_cnt;
uchar target_id;
uchar target_lun;
__le32 data_addr;
__le32 data_cnt;
__le32 sense_addr;
uchar sense_len;
uchar extra_bytes;
} ASC_SCSIQ_1;
typedef struct asc_scsiq_2 {
u32 srb_tag;
uchar target_ix;
uchar flag;
uchar cdb_len;
uchar tag_code;
ushort vm_id;
} ASC_SCSIQ_2;
typedef struct asc_scsiq_3 {
uchar done_stat;
uchar host_stat;
uchar scsi_stat;
uchar scsi_msg;
} ASC_SCSIQ_3;
typedef struct asc_scsiq_4 {
uchar cdb[ASC_MAX_CDB_LEN];
uchar y_first_sg_list_qp;
uchar y_working_sg_qp;
uchar y_working_sg_ix;
uchar y_res;
ushort x_req_count;
ushort x_reconnect_rtn;
__le32 x_saved_data_addr;
__le32 x_saved_data_cnt;
} ASC_SCSIQ_4;
typedef struct asc_q_done_info {
ASC_SCSIQ_2 d2;
ASC_SCSIQ_3 d3;
uchar q_status;
uchar q_no;
uchar cntl;
uchar sense_len;
uchar extra_bytes;
uchar res;
u32 remain_bytes;
} ASC_QDONE_INFO;
typedef struct asc_sg_list {
__le32 addr;
__le32 bytes;
} ASC_SG_LIST;
typedef struct asc_sg_head {
ushort entry_cnt;
ushort queue_cnt;
ushort entry_to_copy;
ushort res;
ASC_SG_LIST sg_list[0];
} ASC_SG_HEAD;
typedef struct asc_scsi_q {
ASC_SCSIQ_1 q1;
ASC_SCSIQ_2 q2;
uchar *cdbptr;
ASC_SG_HEAD *sg_head;
ushort remain_sg_entry_cnt;
ushort next_sg_index;
} ASC_SCSI_Q;
typedef struct asc_scsi_bios_req_q {
ASC_SCSIQ_1 r1;
ASC_SCSIQ_2 r2;
uchar *cdbptr;
ASC_SG_HEAD *sg_head;
uchar *sense_ptr;
ASC_SCSIQ_3 r3;
uchar cdb[ASC_MAX_CDB_LEN];
uchar sense[ASC_MIN_SENSE_LEN];
} ASC_SCSI_BIOS_REQ_Q;
typedef struct asc_risc_q {
uchar fwd;
uchar bwd;
ASC_SCSIQ_1 i1;
ASC_SCSIQ_2 i2;
ASC_SCSIQ_3 i3;
ASC_SCSIQ_4 i4;
} ASC_RISC_Q;
typedef struct asc_sg_list_q {
uchar seq_no;
uchar q_no;
uchar cntl;
uchar sg_head_qp;
uchar sg_list_cnt;
uchar sg_cur_list_cnt;
} ASC_SG_LIST_Q;
typedef struct asc_risc_sg_list_q {
uchar fwd;
uchar bwd;
ASC_SG_LIST_Q sg;
ASC_SG_LIST sg_list[7];
} ASC_RISC_SG_LIST_Q;
#define ASCQ_ERR_Q_STATUS 0x0D
#define ASCQ_ERR_CUR_QNG 0x17
#define ASCQ_ERR_SG_Q_LINKS 0x18
#define ASCQ_ERR_ISR_RE_ENTRY 0x1A
#define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
#define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
/*
* Warning code values are set in ASC_DVC_VAR 'warn_code'.
*/
#define ASC_WARN_NO_ERROR 0x0000
#define ASC_WARN_IO_PORT_ROTATE 0x0001
#define ASC_WARN_EEPROM_CHKSUM 0x0002
#define ASC_WARN_IRQ_MODIFIED 0x0004
#define ASC_WARN_AUTO_CONFIG 0x0008
#define ASC_WARN_CMD_QNG_CONFLICT 0x0010
#define ASC_WARN_EEPROM_RECOVER 0x0020
#define ASC_WARN_CFG_MSW_RECOVER 0x0040
/*
* Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'.
*/
#define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */
#define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
#define ASC_IERR_SET_PC_ADDR 0x0004
#define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
#define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */
#define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */
#define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */
#define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
#define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */
#define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
#define ASC_IERR_NO_BUS_TYPE 0x0400
#define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */
#define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */
#define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */
#define ASC_DEF_MAX_TOTAL_QNG (0xF0)
#define ASC_MIN_TAG_Q_PER_DVC (0x04)
#define ASC_MIN_FREE_Q (0x02)
#define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
#define ASC_MAX_TOTAL_QNG 240
#define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
#define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
#define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
#define ASC_MAX_INRAM_TAG_QNG 16
#define ASC_IOADR_GAP 0x10
#define ASC_SYN_MAX_OFFSET 0x0F
#define ASC_DEF_SDTR_OFFSET 0x0F
#define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
#define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
/* The narrow chip only supports a limited selection of transfer rates.
* These are encoded in the range 0..7 or 0..15 depending whether the chip
* is Ultra-capable or not. These tables let us convert from one to the other.
*/
static const unsigned char asc_syn_xfer_period[8] = {
25, 30, 35, 40, 50, 60, 70, 85
};
static const unsigned char asc_syn_ultra_xfer_period[16] = {
12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
};
typedef struct ext_msg {
uchar msg_type;
uchar msg_len;
uchar msg_req;
union {
struct {
uchar sdtr_xfer_period;
uchar sdtr_req_ack_offset;
} sdtr;
struct {
uchar wdtr_width;
} wdtr;
struct {
uchar mdp_b3;
uchar mdp_b2;
uchar mdp_b1;
uchar mdp_b0;
} mdp;
} u_ext_msg;
uchar res;
} EXT_MSG;
#define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
#define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
#define wdtr_width u_ext_msg.wdtr.wdtr_width
#define mdp_b3 u_ext_msg.mdp_b3
#define mdp_b2 u_ext_msg.mdp_b2
#define mdp_b1 u_ext_msg.mdp_b1
#define mdp_b0 u_ext_msg.mdp_b0
typedef struct asc_dvc_cfg {
ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
ASC_SCSI_BIT_ID_TYPE disc_enable;
ASC_SCSI_BIT_ID_TYPE sdtr_enable;
uchar chip_scsi_id;
uchar isa_dma_speed;
uchar isa_dma_channel;
uchar chip_version;
ushort mcode_date;
ushort mcode_version;
uchar max_tag_qng[ASC_MAX_TID + 1];
uchar sdtr_period_offset[ASC_MAX_TID + 1];
uchar adapter_info[6];
} ASC_DVC_CFG;
#define ASC_DEF_DVC_CNTL 0xFFFF
#define ASC_DEF_CHIP_SCSI_ID 7
#define ASC_DEF_ISA_DMA_SPEED 4
#define ASC_INIT_STATE_BEG_GET_CFG 0x0001
#define ASC_INIT_STATE_END_GET_CFG 0x0002
#define ASC_INIT_STATE_BEG_SET_CFG 0x0004
#define ASC_INIT_STATE_END_SET_CFG 0x0008
#define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
#define ASC_INIT_STATE_END_LOAD_MC 0x0020
#define ASC_INIT_STATE_BEG_INQUIRY 0x0040
#define ASC_INIT_STATE_END_INQUIRY 0x0080
#define ASC_INIT_RESET_SCSI_DONE 0x0100
#define ASC_INIT_STATE_WITHOUT_EEP 0x8000
#define ASC_BUG_FIX_IF_NOT_DWB 0x0001
#define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
#define ASC_MIN_TAGGED_CMD 7
#define ASC_MAX_SCSI_RESET_WAIT 30
#define ASC_OVERRUN_BSIZE 64
struct asc_dvc_var; /* Forward Declaration. */
typedef struct asc_dvc_var {
PortAddr iop_base;
ushort err_code;
ushort dvc_cntl;
ushort bug_fix_cntl;
ushort bus_type;
ASC_SCSI_BIT_ID_TYPE init_sdtr;
ASC_SCSI_BIT_ID_TYPE sdtr_done;
ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
ASC_SCSI_BIT_ID_TYPE unit_not_ready;
ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
ASC_SCSI_BIT_ID_TYPE start_motor;
uchar *overrun_buf;
dma_addr_t overrun_dma;
uchar scsi_reset_wait;
uchar chip_no;
bool is_in_int;
uchar max_total_qng;
uchar cur_total_qng;
uchar in_critical_cnt;
uchar last_q_shortage;
ushort init_state;
uchar cur_dvc_qng[ASC_MAX_TID + 1];
uchar max_dvc_qng[ASC_MAX_TID + 1];
ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
const uchar *sdtr_period_tbl;
ASC_DVC_CFG *cfg;
ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
char redo_scam;
ushort res2;
uchar dos_int13_table[ASC_MAX_TID + 1];
unsigned int max_dma_count;
ASC_SCSI_BIT_ID_TYPE no_scam;
ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
uchar min_sdtr_index;
uchar max_sdtr_index;
struct asc_board *drv_ptr;
unsigned int uc_break;
} ASC_DVC_VAR;
typedef struct asc_dvc_inq_info {
uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
} ASC_DVC_INQ_INFO;
typedef struct asc_cap_info {
u32 lba;
u32 blk_size;
} ASC_CAP_INFO;
typedef struct asc_cap_info_array {
ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
} ASC_CAP_INFO_ARRAY;
#define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
#define ASC_MCNTL_NULL_TARGET (ushort)0x0002
#define ASC_CNTL_INITIATOR (ushort)0x0001
#define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
#define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
#define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
#define ASC_CNTL_NO_SCAM (ushort)0x0010
#define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
#define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
#define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
#define ASC_CNTL_RESET_SCSI (ushort)0x0200
#define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
#define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
#define ASC_CNTL_SCSI_PARITY (ushort)0x1000
#define ASC_CNTL_BURST_MODE (ushort)0x2000
#define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
#define ASC_EEP_DVC_CFG_BEG_VL 2
#define ASC_EEP_MAX_DVC_ADDR_VL 15
#define ASC_EEP_DVC_CFG_BEG 32
#define ASC_EEP_MAX_DVC_ADDR 45
#define ASC_EEP_MAX_RETRY 20
/*
* These macros keep the chip SCSI id and ISA DMA speed
* bitfields in board order. C bitfields aren't portable
* between big and little-endian platforms so they are
* not used.
*/
#define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
#define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
#define ASC_EEP_SET_CHIP_ID(cfg, sid) \
((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
#define ASC_EEP_SET_DMA_SPD(cfg, spd) \
((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
typedef struct asceep_config {
ushort cfg_lsw;
ushort cfg_msw;
uchar init_sdtr;
uchar disc_enable;
uchar use_cmd_qng;
uchar start_motor;
uchar max_total_qng;
uchar max_tag_qng;
uchar bios_scan;
uchar power_up_wait;
uchar no_scam;
uchar id_speed; /* low order 4 bits is chip scsi id */
/* high order 4 bits is isa dma speed */
uchar dos_int13_table[ASC_MAX_TID + 1];
uchar adapter_info[6];
ushort cntl;
ushort chksum;
} ASCEEP_CONFIG;
#define ASC_EEP_CMD_READ 0x80
#define ASC_EEP_CMD_WRITE 0x40
#define ASC_EEP_CMD_WRITE_ABLE 0x30
#define ASC_EEP_CMD_WRITE_DISABLE 0x00
#define ASCV_MSGOUT_BEG 0x0000
#define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
#define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
#define ASCV_BREAK_SAVED_CODE (ushort)0x0006
#define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
#define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
#define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
#define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
#define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
#define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
#define ASCV_BREAK_ADDR (ushort)0x0028
#define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
#define ASCV_BREAK_CONTROL (ushort)0x002C
#define ASCV_BREAK_HIT_COUNT (ushort)0x002E
#define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
#define ASCV_MCODE_CHKSUM_W (ushort)0x0032
#define ASCV_MCODE_SIZE_W (ushort)0x0034
#define ASCV_STOP_CODE_B (ushort)0x0036
#define ASCV_DVC_ERR_CODE_B (ushort)0x0037
#define ASCV_OVERRUN_PADDR_D (ushort)0x0038
#define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
#define ASCV_HALTCODE_W (ushort)0x0040
#define ASCV_CHKSUM_W (ushort)0x0042
#define ASCV_MC_DATE_W (ushort)0x0044
#define ASCV_MC_VER_W (ushort)0x0046
#define ASCV_NEXTRDY_B (ushort)0x0048
#define ASCV_DONENEXT_B (ushort)0x0049
#define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
#define ASCV_SCSIBUSY_B (ushort)0x004B
#define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
#define ASCV_CURCDB_B (ushort)0x004D
#define ASCV_RCLUN_B (ushort)0x004E
#define ASCV_BUSY_QHEAD_B (ushort)0x004F
#define ASCV_DISC1_QHEAD_B (ushort)0x0050
#define ASCV_DISC_ENABLE_B (ushort)0x0052
#define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
#define ASCV_HOSTSCSI_ID_B (ushort)0x0055
#define ASCV_MCODE_CNTL_B (ushort)0x0056
#define ASCV_NULL_TARGET_B (ushort)0x0057
#define ASCV_FREE_Q_HEAD_W (ushort)0x0058
#define ASCV_DONE_Q_TAIL_W (ushort)0x005A
#define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
#define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
#define ASCV_HOST_FLAG_B (ushort)0x005D
#define ASCV_TOTAL_READY_Q_B (ushort)0x0064
#define ASCV_VER_SERIAL_B (ushort)0x0065
#define ASCV_HALTCODE_SAVED_W (ushort)0x0066
#define ASCV_WTM_FLAG_B (ushort)0x0068
#define ASCV_RISC_FLAG_B (ushort)0x006A
#define ASCV_REQ_SG_LIST_QP (ushort)0x006B
#define ASC_HOST_FLAG_IN_ISR 0x01
#define ASC_HOST_FLAG_ACK_INT 0x02
#define ASC_RISC_FLAG_GEN_INT 0x01
#define ASC_RISC_FLAG_REQ_SG_LIST 0x02
#define IOP_CTRL (0x0F)
#define IOP_STATUS (0x0E)
#define IOP_INT_ACK IOP_STATUS
#define IOP_REG_IFC (0x0D)
#define IOP_SYN_OFFSET (0x0B)
#define IOP_EXTRA_CONTROL (0x0D)
#define IOP_REG_PC (0x0C)
#define IOP_RAM_ADDR (0x0A)
#define IOP_RAM_DATA (0x08)
#define IOP_EEP_DATA (0x06)
#define IOP_EEP_CMD (0x07)
#define IOP_VERSION (0x03)
#define IOP_CONFIG_HIGH (0x04)
#define IOP_CONFIG_LOW (0x02)
#define IOP_SIG_BYTE (0x01)
#define IOP_SIG_WORD (0x00)
#define IOP_REG_DC1 (0x0E)
#define IOP_REG_DC0 (0x0C)
#define IOP_REG_SB (0x0B)
#define IOP_REG_DA1 (0x0A)
#define IOP_REG_DA0 (0x08)
#define IOP_REG_SC (0x09)
#define IOP_DMA_SPEED (0x07)
#define IOP_REG_FLAG (0x07)
#define IOP_FIFO_H (0x06)
#define IOP_FIFO_L (0x04)
#define IOP_REG_ID (0x05)
#define IOP_REG_QP (0x03)
#define IOP_REG_IH (0x02)
#define IOP_REG_IX (0x01)
#define IOP_REG_AX (0x00)
#define IFC_REG_LOCK (0x00)
#define IFC_REG_UNLOCK (0x09)
#define IFC_WR_EN_FILTER (0x10)
#define IFC_RD_NO_EEPROM (0x10)
#define IFC_SLEW_RATE (0x20)
#define IFC_ACT_NEG (0x40)
#define IFC_INP_FILTER (0x80)
#define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
#define SC_SEL (uchar)(0x80)
#define SC_BSY (uchar)(0x40)
#define SC_ACK (uchar)(0x20)
#define SC_REQ (uchar)(0x10)
#define SC_ATN (uchar)(0x08)
#define SC_IO (uchar)(0x04)
#define SC_CD (uchar)(0x02)
#define SC_MSG (uchar)(0x01)
#define SEC_SCSI_CTL (uchar)(0x80)
#define SEC_ACTIVE_NEGATE (uchar)(0x40)
#define SEC_SLEW_RATE (uchar)(0x20)
#define SEC_ENABLE_FILTER (uchar)(0x10)
#define ASC_HALT_EXTMSG_IN (ushort)0x8000
#define ASC_HALT_CHK_CONDITION (ushort)0x8100
#define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
#define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
#define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
#define ASC_HALT_SDTR_REJECTED (ushort)0x4000
#define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
#define ASC_MAX_QNO 0xF8
#define ASC_DATA_SEC_BEG (ushort)0x0080
#define ASC_DATA_SEC_END (ushort)0x0080
#define ASC_CODE_SEC_BEG (ushort)0x0080
#define ASC_CODE_SEC_END (ushort)0x0080
#define ASC_QADR_BEG (0x4000)
#define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
#define ASC_QADR_END (ushort)0x7FFF
#define ASC_QLAST_ADR (ushort)0x7FC0
#define ASC_QBLK_SIZE 0x40
#define ASC_BIOS_DATA_QBEG 0xF8
#define ASC_MIN_ACTIVE_QNO 0x01
#define ASC_QLINK_END 0xFF
#define ASC_EEPROM_WORDS 0x10
#define ASC_MAX_MGS_LEN 0x10
#define ASC_BIOS_ADDR_DEF 0xDC00
#define ASC_BIOS_SIZE 0x3800
#define ASC_BIOS_RAM_OFF 0x3800
#define ASC_BIOS_RAM_SIZE 0x800
#define ASC_BIOS_MIN_ADDR 0xC000
#define ASC_BIOS_MAX_ADDR 0xEC00
#define ASC_BIOS_BANK_SIZE 0x0400
#define ASC_MCODE_START_ADDR 0x0080
#define ASC_CFG0_HOST_INT_ON 0x0020
#define ASC_CFG0_BIOS_ON 0x0040
#define ASC_CFG0_VERA_BURST_ON 0x0080
#define ASC_CFG0_SCSI_PARITY_ON 0x0800
#define ASC_CFG1_SCSI_TARGET_ON 0x0080
#define ASC_CFG1_LRAM_8BITS_ON 0x0800
#define ASC_CFG_MSW_CLR_MASK 0x3080
#define CSW_TEST1 (ASC_CS_TYPE)0x8000
#define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
#define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
#define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
#define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
#define CSW_TEST2 (ASC_CS_TYPE)0x0400
#define CSW_TEST3 (ASC_CS_TYPE)0x0200
#define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
#define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
#define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
#define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
#define CSW_HALTED (ASC_CS_TYPE)0x0010
#define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
#define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
#define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
#define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
#define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
#define CIW_INT_ACK (ASC_CS_TYPE)0x0100
#define CIW_TEST1 (ASC_CS_TYPE)0x0200
#define CIW_TEST2 (ASC_CS_TYPE)0x0400
#define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
#define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
#define CC_CHIP_RESET (uchar)0x80
#define CC_SCSI_RESET (uchar)0x40
#define CC_HALT (uchar)0x20
#define CC_SINGLE_STEP (uchar)0x10
#define CC_DMA_ABLE (uchar)0x08
#define CC_TEST (uchar)0x04
#define CC_BANK_ONE (uchar)0x02
#define CC_DIAG (uchar)0x01
#define ASC_1000_ID0W 0x04C1
#define ASC_1000_ID0W_FIX 0x00C1
#define ASC_1000_ID1B 0x25
#define ASC_EISA_REV_IOP_MASK (0x0C83)
#define ASC_EISA_CFG_IOP_MASK (0x0C86)
#define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
#define INS_HALTINT (ushort)0x6281
#define INS_HALT (ushort)0x6280
#define INS_SINT (ushort)0x6200
#define INS_RFLAG_WTM (ushort)0x7380
#define ASC_MC_SAVE_CODE_WSIZE 0x500
#define ASC_MC_SAVE_DATA_WSIZE 0x40
typedef struct asc_mc_saved {
ushort data[ASC_MC_SAVE_DATA_WSIZE];
ushort code[ASC_MC_SAVE_CODE_WSIZE];
} ASC_MC_SAVED;
#define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
#define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
#define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
#define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
#define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
#define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
#define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
#define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
#define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
#define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
#define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
#define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
#define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
#define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
#define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
#define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
#define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
#define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
#define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
#define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
#define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
#define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
#define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
#define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
#define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
#define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
#define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
#define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
#define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
#define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
#define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
#define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
#define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
#define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
#define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
#define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
#define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
#define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
#define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
#define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
#define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
#define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
#define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
#define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
#define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
#define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
#define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
#define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
#define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
#define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
#define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
#define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
#define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
#define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
#define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
#define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
#define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
#define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
#define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
#define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
#define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
#define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
#define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
#define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
#define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
#define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
#define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
#define AdvPortAddr void __iomem * /* Virtual memory address size */
/*
* Define Adv Library required memory access macros.
*/
#define ADV_MEM_READB(addr) readb(addr)
#define ADV_MEM_READW(addr) readw(addr)
#define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
#define ADV_MEM_WRITEW(addr, word) writew(word, addr)
#define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
/*
* Define total number of simultaneous maximum element scatter-gather
* request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
* maximum number of outstanding commands per wide host adapter. Each
* command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
* elements. Allow each command to have at least one ADV_SG_BLOCK structure.
* This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
* structures or 255 scatter-gather elements.
*/
#define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
/*
* Define maximum number of scatter-gather elements per request.
*/
#define ADV_MAX_SG_LIST 255
#define NO_OF_SG_PER_BLOCK 15
#define ADV_EEP_DVC_CFG_BEGIN (0x00)
#define ADV_EEP_DVC_CFG_END (0x15)
#define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
#define ADV_EEP_MAX_WORD_ADDR (0x1E)
#define ADV_EEP_DELAY_MS 100
#define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
#define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
/*
* For the ASC3550 Bit 13 is Termination Polarity control bit.
* For later ICs Bit 13 controls whether the CIS (Card Information
* Service Section) is loaded from EEPROM.
*/
#define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
#define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
/*
* ASC38C1600 Bit 11
*
* If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
* INT A in the PCI Configuration Space Int Pin field. If it is 1, then
* Function 0 will specify INT B.
*
* If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
* INT B in the PCI Configuration Space Int Pin field. If it is 1, then
* Function 1 will specify INT A.
*/
#define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
typedef struct adveep_3550_config {
/* Word Offset, Description */
ushort cfg_lsw; /* 00 power up initialization */
/* bit 13 set - Term Polarity Control */
/* bit 14 set - BIOS Enable */
/* bit 15 set - Big Endian Mode */
ushort cfg_msw; /* 01 unused */
ushort disc_enable; /* 02 disconnect enable */
ushort wdtr_able; /* 03 Wide DTR able */
ushort sdtr_able; /* 04 Synchronous DTR able */
ushort start_motor; /* 05 send start up motor */
ushort tagqng_able; /* 06 tag queuing able */
ushort bios_scan; /* 07 BIOS device control */
ushort scam_tolerant; /* 08 no scam */
uchar adapter_scsi_id; /* 09 Host Adapter ID */
uchar bios_boot_delay; /* power up wait */
uchar scsi_reset_delay; /* 10 reset delay */
uchar bios_id_lun; /* first boot device scsi id & lun */
/* high nibble is lun */
/* low nibble is scsi id */
uchar termination; /* 11 0 - automatic */
/* 1 - low off / high off */
/* 2 - low off / high on */
/* 3 - low on / high on */
/* There is no low on / high off */
uchar reserved1; /* reserved byte (not used) */
ushort bios_ctrl; /* 12 BIOS control bits */
/* bit 0 BIOS don't act as initiator. */
/* bit 1 BIOS > 1 GB support */
/* bit 2 BIOS > 2 Disk Support */
/* bit 3 BIOS don't support removables */
/* bit 4 BIOS support bootable CD */
/* bit 5 BIOS scan enabled */
/* bit 6 BIOS support multiple LUNs */
/* bit 7 BIOS display of message */
/* bit 8 SCAM disabled */
/* bit 9 Reset SCSI bus during init. */
/* bit 10 */
/* bit 11 No verbose initialization. */
/* bit 12 SCSI parity enabled */
/* bit 13 */
/* bit 14 */
/* bit 15 */
ushort ultra_able; /* 13 ULTRA speed able */
ushort reserved2; /* 14 reserved */
uchar max_host_qng; /* 15 maximum host queuing */
uchar max_dvc_qng; /* maximum per device queuing */
ushort dvc_cntl; /* 16 control bit for driver */
ushort bug_fix; /* 17 control bit for bug fix */
ushort serial_number_word1; /* 18 Board serial number word 1 */
ushort serial_number_word2; /* 19 Board serial number word 2 */
ushort serial_number_word3; /* 20 Board serial number word 3 */
ushort check_sum; /* 21 EEP check sum */
uchar oem_name[16]; /* 22 OEM name */
ushort dvc_err_code; /* 30 last device driver error code */
ushort adv_err_code; /* 31 last uc and Adv Lib error code */
ushort adv_err_addr; /* 32 last uc error address */
ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
ushort saved_adv_err_addr; /* 35 saved last uc error address */
ushort num_of_err; /* 36 number of error */
} ADVEEP_3550_CONFIG;
typedef struct adveep_38C0800_config {
/* Word Offset, Description */
ushort cfg_lsw; /* 00 power up initialization */
/* bit 13 set - Load CIS */
/* bit 14 set - BIOS Enable */
/* bit 15 set - Big Endian Mode */
ushort cfg_msw; /* 01 unused */
ushort disc_enable; /* 02 disconnect enable */
ushort wdtr_able; /* 03 Wide DTR able */
ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
ushort start_motor; /* 05 send start up motor */
ushort tagqng_able; /* 06 tag queuing able */
ushort bios_scan; /* 07 BIOS device control */
ushort scam_tolerant; /* 08 no scam */
uchar adapter_scsi_id; /* 09 Host Adapter ID */
uchar bios_boot_delay; /* power up wait */
uchar scsi_reset_delay; /* 10 reset delay */
uchar bios_id_lun; /* first boot device scsi id & lun */
/* high nibble is lun */
/* low nibble is scsi id */
uchar termination_se; /* 11 0 - automatic */
/* 1 - low off / high off */
/* 2 - low off / high on */
/* 3 - low on / high on */
/* There is no low on / high off */
uchar termination_lvd; /* 11 0 - automatic */
/* 1 - low off / high off */
/* 2 - low off / high on */
/* 3 - low on / high on */
/* There is no low on / high off */
ushort bios_ctrl; /* 12 BIOS control bits */
/* bit 0 BIOS don't act as initiator. */
/* bit 1 BIOS > 1 GB support */
/* bit 2 BIOS > 2 Disk Support */
/* bit 3 BIOS don't support removables */
/* bit 4 BIOS support bootable CD */
/* bit 5 BIOS scan enabled */
/* bit 6 BIOS support multiple LUNs */
/* bit 7 BIOS display of message */
/* bit 8 SCAM disabled */
/* bit 9 Reset SCSI bus during init. */
/* bit 10 */
/* bit 11 No verbose initialization. */
/* bit 12 SCSI parity enabled */
/* bit 13 */
/* bit 14 */
/* bit 15 */
ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
uchar max_host_qng; /* 15 maximum host queueing */
uchar max_dvc_qng; /* maximum per device queuing */
ushort dvc_cntl; /* 16 control bit for driver */
ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
ushort serial_number_word1; /* 18 Board serial number word 1 */
ushort serial_number_word2; /* 19 Board serial number word 2 */
ushort serial_number_word3; /* 20 Board serial number word 3 */
ushort check_sum; /* 21 EEP check sum */
uchar oem_name[16]; /* 22 OEM name */
ushort dvc_err_code; /* 30 last device driver error code */
ushort adv_err_code; /* 31 last uc and Adv Lib error code */
ushort adv_err_addr; /* 32 last uc error address */
ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
ushort saved_adv_err_addr; /* 35 saved last uc error address */
ushort reserved36; /* 36 reserved */
ushort reserved37; /* 37 reserved */
ushort reserved38; /* 38 reserved */
ushort reserved39; /* 39 reserved */
ushort reserved40; /* 40 reserved */
ushort reserved41; /* 41 reserved */
ushort reserved42; /* 42 reserved */
ushort reserved43; /* 43 reserved */
ushort reserved44; /* 44 reserved */
ushort reserved45; /* 45 reserved */
ushort reserved46; /* 46 reserved */
ushort reserved47; /* 47 reserved */
ushort reserved48; /* 48 reserved */
ushort reserved49; /* 49 reserved */
ushort reserved50; /* 50 reserved */
ushort reserved51; /* 51 reserved */
ushort reserved52; /* 52 reserved */
ushort reserved53; /* 53 reserved */
ushort reserved54; /* 54 reserved */
ushort reserved55; /* 55 reserved */
ushort cisptr_lsw; /* 56 CIS PTR LSW */
ushort cisprt_msw; /* 57 CIS PTR MSW */
ushort subsysvid; /* 58 SubSystem Vendor ID */
ushort subsysid; /* 59 SubSystem ID */
ushort reserved60; /* 60 reserved */
ushort reserved61; /* 61 reserved */
ushort reserved62; /* 62 reserved */
ushort reserved63; /* 63 reserved */
} ADVEEP_38C0800_CONFIG;
typedef struct adveep_38C1600_config {
/* Word Offset, Description */
ushort cfg_lsw; /* 00 power up initialization */
/* bit 11 set - Func. 0 INTB, Func. 1 INTA */
/* clear - Func. 0 INTA, Func. 1 INTB */
/* bit 13 set - Load CIS */
/* bit 14 set - BIOS Enable */
/* bit 15 set - Big Endian Mode */
ushort cfg_msw; /* 01 unused */
ushort disc_enable; /* 02 disconnect enable */
ushort wdtr_able; /* 03 Wide DTR able */
ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
ushort start_motor; /* 05 send start up motor */
ushort tagqng_able; /* 06 tag queuing able */
ushort bios_scan; /* 07 BIOS device control */
ushort scam_tolerant; /* 08 no scam */
uchar adapter_scsi_id; /* 09 Host Adapter ID */
uchar bios_boot_delay; /* power up wait */
uchar scsi_reset_delay; /* 10 reset delay */
uchar bios_id_lun; /* first boot device scsi id & lun */
/* high nibble is lun */
/* low nibble is scsi id */
uchar termination_se; /* 11 0 - automatic */
/* 1 - low off / high off */
/* 2 - low off / high on */
/* 3 - low on / high on */
/* There is no low on / high off */
uchar termination_lvd; /* 11 0 - automatic */
/* 1 - low off / high off */
/* 2 - low off / high on */
/* 3 - low on / high on */
/* There is no low on / high off */
ushort bios_ctrl; /* 12 BIOS control bits */
/* bit 0 BIOS don't act as initiator. */
/* bit 1 BIOS > 1 GB support */
/* bit 2 BIOS > 2 Disk Support */
/* bit 3 BIOS don't support removables */
/* bit 4 BIOS support bootable CD */
/* bit 5 BIOS scan enabled */
/* bit 6 BIOS support multiple LUNs */
/* bit 7 BIOS display of message */
/* bit 8 SCAM disabled */
/* bit 9 Reset SCSI bus during init. */
/* bit 10 Basic Integrity Checking disabled */
/* bit 11 No verbose initialization. */
/* bit 12 SCSI parity enabled */
/* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
/* bit 14 */
/* bit 15 */
ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
uchar max_host_qng; /* 15 maximum host queueing */
uchar max_dvc_qng; /* maximum per device queuing */
ushort dvc_cntl; /* 16 control bit for driver */
ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
ushort serial_number_word1; /* 18 Board serial number word 1 */
ushort serial_number_word2; /* 19 Board serial number word 2 */
ushort serial_number_word3; /* 20 Board serial number word 3 */
ushort check_sum; /* 21 EEP check sum */
uchar oem_name[16]; /* 22 OEM name */
ushort dvc_err_code; /* 30 last device driver error code */
ushort adv_err_code; /* 31 last uc and Adv Lib error code */
ushort adv_err_addr; /* 32 last uc error address */
ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
ushort saved_adv_err_addr; /* 35 saved last uc error address */
ushort reserved36; /* 36 reserved */
ushort reserved37; /* 37 reserved */
ushort reserved38; /* 38 reserved */
ushort reserved39; /* 39 reserved */
ushort reserved40; /* 40 reserved */
ushort reserved41; /* 41 reserved */
ushort reserved42; /* 42 reserved */
ushort reserved43; /* 43 reserved */
ushort reserved44; /* 44 reserved */
ushort reserved45; /* 45 reserved */
ushort reserved46; /* 46 reserved */
ushort reserved47; /* 47 reserved */
ushort reserved48; /* 48 reserved */
ushort reserved49; /* 49 reserved */
ushort reserved50; /* 50 reserved */
ushort reserved51; /* 51 reserved */
ushort reserved52; /* 52 reserved */
ushort reserved53; /* 53 reserved */
ushort reserved54; /* 54 reserved */
ushort reserved55; /* 55 reserved */
ushort cisptr_lsw; /* 56 CIS PTR LSW */
ushort cisprt_msw; /* 57 CIS PTR MSW */
ushort subsysvid; /* 58 SubSystem Vendor ID */
ushort subsysid; /* 59 SubSystem ID */
ushort reserved60; /* 60 reserved */
ushort reserved61; /* 61 reserved */
ushort reserved62; /* 62 reserved */
ushort reserved63; /* 63 reserved */
} ADVEEP_38C1600_CONFIG;
/*
* EEPROM Commands
*/
#define ASC_EEP_CMD_DONE 0x0200
/* bios_ctrl */
#define BIOS_CTRL_BIOS 0x0001
#define BIOS_CTRL_EXTENDED_XLAT 0x0002
#define BIOS_CTRL_GT_2_DISK 0x0004
#define BIOS_CTRL_BIOS_REMOVABLE 0x0008
#define BIOS_CTRL_BOOTABLE_CD 0x0010
#define BIOS_CTRL_MULTIPLE_LUN 0x0040
#define BIOS_CTRL_DISPLAY_MSG 0x0080
#define BIOS_CTRL_NO_SCAM 0x0100
#define BIOS_CTRL_RESET_SCSI_BUS 0x0200
#define BIOS_CTRL_INIT_VERBOSE 0x0800
#define BIOS_CTRL_SCSI_PARITY 0x1000
#define BIOS_CTRL_AIPP_DIS 0x2000
#define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
#define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
/*
* XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
* a special 16K Adv Library and Microcode version. After the issue is
* resolved, should restore 32K support.
*
* #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
*/
#define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
/*
* Byte I/O register address from base of 'iop_base'.
*/
#define IOPB_INTR_STATUS_REG 0x00
#define IOPB_CHIP_ID_1 0x01
#define IOPB_INTR_ENABLES 0x02
#define IOPB_CHIP_TYPE_REV 0x03
#define IOPB_RES_ADDR_4 0x04
#define IOPB_RES_ADDR_5 0x05
#define IOPB_RAM_DATA 0x06
#define IOPB_RES_ADDR_7 0x07
#define IOPB_FLAG_REG 0x08
#define IOPB_RES_ADDR_9 0x09
#define IOPB_RISC_CSR 0x0A
#define IOPB_RES_ADDR_B 0x0B
#define IOPB_RES_ADDR_C 0x0C
#define IOPB_RES_ADDR_D 0x0D
#define IOPB_SOFT_OVER_WR 0x0E
#define IOPB_RES_ADDR_F 0x0F
#define IOPB_MEM_CFG 0x10
#define IOPB_RES_ADDR_11 0x11
#define IOPB_GPIO_DATA 0x12
#define IOPB_RES_ADDR_13 0x13
#define IOPB_FLASH_PAGE 0x14
#define IOPB_RES_ADDR_15 0x15
#define IOPB_GPIO_CNTL 0x16
#define IOPB_RES_ADDR_17 0x17
#define IOPB_FLASH_DATA 0x18
#define IOPB_RES_ADDR_19 0x19
#define IOPB_RES_ADDR_1A 0x1A
#define IOPB_RES_ADDR_1B 0x1B
#define IOPB_RES_ADDR_1C 0x1C
#define IOPB_RES_ADDR_1D 0x1D
#define IOPB_RES_ADDR_1E 0x1E
#define IOPB_RES_ADDR_1F 0x1F
#define IOPB_DMA_CFG0 0x20
#define IOPB_DMA_CFG1 0x21
#define IOPB_TICKLE 0x22
#define IOPB_DMA_REG_WR 0x23
#define IOPB_SDMA_STATUS 0x24
#define IOPB_SCSI_BYTE_CNT 0x25
#define IOPB_HOST_BYTE_CNT 0x26
#define IOPB_BYTE_LEFT_TO_XFER 0x27
#define IOPB_BYTE_TO_XFER_0 0x28
#define IOPB_BYTE_TO_XFER_1 0x29
#define IOPB_BYTE_TO_XFER_2 0x2A
#define IOPB_BYTE_TO_XFER_3 0x2B
#define IOPB_ACC_GRP 0x2C
#define IOPB_RES_ADDR_2D 0x2D
#define IOPB_DEV_ID 0x2E
#define IOPB_RES_ADDR_2F 0x2F
#define IOPB_SCSI_DATA 0x30
#define IOPB_RES_ADDR_31 0x31
#define IOPB_RES_ADDR_32 0x32
#define IOPB_SCSI_DATA_HSHK 0x33
#define IOPB_SCSI_CTRL 0x34
#define IOPB_RES_ADDR_35 0x35
#define IOPB_RES_ADDR_36 0x36
#define IOPB_RES_ADDR_37 0x37
#define IOPB_RAM_BIST 0x38
#define IOPB_PLL_TEST 0x39
#define IOPB_PCI_INT_CFG 0x3A
#define IOPB_RES_ADDR_3B 0x3B
#define IOPB_RFIFO_CNT 0x3C
#define IOPB_RES_ADDR_3D 0x3D
#define IOPB_RES_ADDR_3E 0x3E
#define IOPB_RES_ADDR_3F 0x3F
/*
* Word I/O register address from base of 'iop_base'.
*/
#define IOPW_CHIP_ID_0 0x00 /* CID0 */
#define IOPW_CTRL_REG 0x02 /* CC */
#define IOPW_RAM_ADDR 0x04 /* LA */
#define IOPW_RAM_DATA 0x06 /* LD */
#define IOPW_RES_ADDR_08 0x08
#define IOPW_RISC_CSR 0x0A /* CSR */
#define IOPW_SCSI_CFG0 0x0C /* CFG0 */
#define IOPW_SCSI_CFG1 0x0E /* CFG1 */
#define IOPW_RES_ADDR_10 0x10
#define IOPW_SEL_MASK 0x12 /* SM */
#define IOPW_RES_ADDR_14 0x14
#define IOPW_FLASH_ADDR 0x16 /* FA */
#define IOPW_RES_ADDR_18 0x18
#define IOPW_EE_CMD 0x1A /* EC */
#define IOPW_EE_DATA 0x1C /* ED */
#define IOPW_SFIFO_CNT 0x1E /* SFC */
#define IOPW_RES_ADDR_20 0x20
#define IOPW_Q_BASE 0x22 /* QB */
#define IOPW_QP 0x24 /* QP */
#define IOPW_IX 0x26 /* IX */
#define IOPW_SP 0x28 /* SP */
#define IOPW_PC 0x2A /* PC */
#define IOPW_RES_ADDR_2C 0x2C
#define IOPW_RES_ADDR_2E 0x2E
#define IOPW_SCSI_DATA 0x30 /* SD */
#define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
#define IOPW_SCSI_CTRL 0x34 /* SC */
#define IOPW_HSHK_CFG 0x36 /* HCFG */
#define IOPW_SXFR_STATUS 0x36 /* SXS */
#define IOPW_SXFR_CNTL 0x38 /* SXL */
#define IOPW_SXFR_CNTH 0x3A /* SXH */
#define IOPW_RES_ADDR_3C 0x3C
#define IOPW_RFIFO_DATA 0x3E /* RFD */
/*
* Doubleword I/O register address from base of 'iop_base'.
*/
#define IOPDW_RES_ADDR_0 0x00
#define IOPDW_RAM_DATA 0x04
#define IOPDW_RES_ADDR_8 0x08
#define IOPDW_RES_ADDR_C 0x0C
#define IOPDW_RES_ADDR_10 0x10
#define IOPDW_COMMA 0x14
#define IOPDW_COMMB 0x18
#define IOPDW_RES_ADDR_1C 0x1C
#define IOPDW_SDMA_ADDR0 0x20
#define IOPDW_SDMA_ADDR1 0x24
#define IOPDW_SDMA_COUNT 0x28
#define IOPDW_SDMA_ERROR 0x2C
#define IOPDW_RDMA_ADDR0 0x30
#define IOPDW_RDMA_ADDR1 0x34
#define IOPDW_RDMA_COUNT 0x38
#define IOPDW_RDMA_ERROR 0x3C
#define ADV_CHIP_ID_BYTE 0x25
#define ADV_CHIP_ID_WORD 0x04C1
#define ADV_INTR_ENABLE_HOST_INTR 0x01
#define ADV_INTR_ENABLE_SEL_INTR 0x02
#define ADV_INTR_ENABLE_DPR_INTR 0x04
#define ADV_INTR_ENABLE_RTA_INTR 0x08
#define ADV_INTR_ENABLE_RMA_INTR 0x10
#define ADV_INTR_ENABLE_RST_INTR 0x20
#define ADV_INTR_ENABLE_DPE_INTR 0x40
#define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
#define ADV_INTR_STATUS_INTRA 0x01
#define ADV_INTR_STATUS_INTRB 0x02
#define ADV_INTR_STATUS_INTRC 0x04
#define ADV_RISC_CSR_STOP (0x0000)
#define ADV_RISC_TEST_COND (0x2000)
#define ADV_RISC_CSR_RUN (0x4000)
#define ADV_RISC_CSR_SINGLE_STEP (0x8000)
#define ADV_CTRL_REG_HOST_INTR 0x0100
#define ADV_CTRL_REG_SEL_INTR 0x0200
#define ADV_CTRL_REG_DPR_INTR 0x0400
#define ADV_CTRL_REG_RTA_INTR 0x0800
#define ADV_CTRL_REG_RMA_INTR 0x1000
#define ADV_CTRL_REG_RES_BIT14 0x2000
#define ADV_CTRL_REG_DPE_INTR 0x4000
#define ADV_CTRL_REG_POWER_DONE 0x8000
#define ADV_CTRL_REG_ANY_INTR 0xFF00
#define ADV_CTRL_REG_CMD_RESET 0x00C6
#define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
#define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
#define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
#define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
#define ADV_TICKLE_NOP 0x00
#define ADV_TICKLE_A 0x01
#define ADV_TICKLE_B 0x02
#define ADV_TICKLE_C 0x03
#define AdvIsIntPending(port) \
(AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
/*
* SCSI_CFG0 Register bit definitions
*/
#define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
#define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
#define EVEN_PARITY 0x1000 /* Select Even Parity */
#define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
#define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
#define PRIM_MODE 0x0100 /* Primitive SCSI mode */
#define SCAM_EN 0x0080 /* Enable SCAM selection */
#define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
#define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
#define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
#define OUR_ID 0x000F /* SCSI ID */
/*
* SCSI_CFG1 Register bit definitions
*/
#define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
#define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
#define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
#define FILTER_SEL 0x0C00 /* Filter Period Selection */
#define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
#define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
#define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
#define ACTIVE_DBL 0x0200 /* Disable Active Negation */
#define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
#define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
#define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
#define TERM_CTL 0x0030 /* External SCSI Termination Bits */
#define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
#define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
#define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
/*
* Addendum for ASC-38C0800 Chip
*
* The ASC-38C1600 Chip uses the same definitions except that the
* bus mode override bits [12:10] have been moved to byte register
* offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
* SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
* is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
* Also each ASC-38C1600 function or channel uses only cable bits [5:4]
* and [1:0]. Bits [14], [7:6], [3:2] are unused.
*/
#define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
#define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
#define HVD 0x1000 /* HVD Device Detect */
#define LVD 0x0800 /* LVD Device Detect */
#define SE 0x0400 /* SE Device Detect */
#define TERM_LVD 0x00C0 /* LVD Termination Bits */
#define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
#define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
#define TERM_SE 0x0030 /* SE Termination Bits */
#define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
#define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
#define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
#define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
#define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
#define C_DET_SE 0x0003 /* SE Cable Detect Bits */
#define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
#define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
#define CABLE_ILLEGAL_A 0x7
/* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
#define CABLE_ILLEGAL_B 0xB
/* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
/*
* MEM_CFG Register bit definitions
*/
#define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
#define FAST_EE_CLK 0x20 /* Diagnostic Bit */
#define RAM_SZ 0x1C /* Specify size of RAM to RISC */
#define RAM_SZ_2KB 0x00 /* 2 KB */
#define RAM_SZ_4KB 0x04 /* 4 KB */
#define RAM_SZ_8KB 0x08 /* 8 KB */
#define RAM_SZ_16KB 0x0C /* 16 KB */
#define RAM_SZ_32KB 0x10 /* 32 KB */
#define RAM_SZ_64KB 0x14 /* 64 KB */
/*
* DMA_CFG0 Register bit definitions
*
* This register is only accessible to the host.
*/
#define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
#define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
#define FIFO_THRESH_16B 0x00 /* 16 bytes */
#define FIFO_THRESH_32B 0x20 /* 32 bytes */
#define FIFO_THRESH_48B 0x30 /* 48 bytes */
#define FIFO_THRESH_64B 0x40 /* 64 bytes */
#define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
#define FIFO_THRESH_96B 0x60 /* 96 bytes */
#define FIFO_THRESH_112B 0x70 /* 112 bytes */
#define START_CTL 0x0C /* DMA start conditions */
#define START_CTL_TH 0x00 /* Wait threshold level (default) */
#define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
#define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
#define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
#define READ_CMD 0x03 /* Memory Read Method */
#define READ_CMD_MR 0x00 /* Memory Read */
#define READ_CMD_MRL 0x02 /* Memory Read Long */
#define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
/*
* ASC-38C0800 RAM BIST Register bit definitions
*/
#define RAM_TEST_MODE 0x80
#define PRE_TEST_MODE 0x40
#define NORMAL_MODE 0x00
#define RAM_TEST_DONE 0x10
#define RAM_TEST_STATUS 0x0F
#define RAM_TEST_HOST_ERROR 0x08
#define RAM_TEST_INTRAM_ERROR 0x04
#define RAM_TEST_RISC_ERROR 0x02
#define RAM_TEST_SCSI_ERROR 0x01
#define RAM_TEST_SUCCESS 0x00
#define PRE_TEST_VALUE 0x05
#define NORMAL_VALUE 0x00
/*
* ASC38C1600 Definitions
*
* IOPB_PCI_INT_CFG Bit Field Definitions
*/
#define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
/*
* Bit 1 can be set to change the interrupt for the Function to operate in
* Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
* Open Drain mode. Both functions of the ASC38C1600 must be set to the same
* mode, otherwise the operating mode is undefined.
*/
#define TOTEMPOLE 0x02
/*
* Bit 0 can be used to change the Int Pin for the Function. The value is
* 0 by default for both Functions with Function 0 using INT A and Function
* B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
* INT A is used.
*
* EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
* value specified in the PCI Configuration Space.
*/
#define INTAB 0x01
/*
* Adv Library Status Definitions
*/
#define ADV_TRUE 1
#define ADV_FALSE 0
#define ADV_SUCCESS 1
#define ADV_BUSY 0
#define ADV_ERROR (-1)
/*
* ADV_DVC_VAR 'warn_code' values
*/
#define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
#define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
#define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
#define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
#define ADV_MAX_TID 15 /* max. target identifier */
#define ADV_MAX_LUN 7 /* max. logical unit number */
/*
* Fixed locations of microcode operating variables.
*/
#define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
#define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
#define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
#define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
#define ASC_MC_VERSION_NUM 0x003A /* microcode number */
#define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
#define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
#define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
#define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
#define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
#define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
#define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
#define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
#define ASC_MC_CHIP_TYPE 0x009A
#define ASC_MC_INTRB_CODE 0x009B
#define ASC_MC_WDTR_ABLE 0x009C
#define ASC_MC_SDTR_ABLE 0x009E
#define ASC_MC_TAGQNG_ABLE 0x00A0
#define ASC_MC_DISC_ENABLE 0x00A2
#define ASC_MC_IDLE_CMD_STATUS 0x00A4
#define ASC_MC_IDLE_CMD 0x00A6
#define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
#define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
#define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
#define ASC_MC_DEFAULT_MEM_CFG 0x00B0
#define ASC_MC_DEFAULT_SEL_MASK 0x00B2
#define ASC_MC_SDTR_DONE 0x00B6
#define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
#define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
#define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
#define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
#define ASC_MC_WDTR_DONE 0x0124
#define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
#define ASC_MC_ICQ 0x0160
#define ASC_MC_IRQ 0x0164
#define ASC_MC_PPR_ABLE 0x017A
/*
* BIOS LRAM variable absolute offsets.
*/
#define BIOS_CODESEG 0x54
#define BIOS_CODELEN 0x56
#define BIOS_SIGNATURE 0x58
#define BIOS_VERSION 0x5A
/*
* Microcode Control Flags
*
* Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
* and handled by the microcode.
*/
#define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
#define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
/*
* ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
*/
#define HSHK_CFG_WIDE_XFR 0x8000
#define HSHK_CFG_RATE 0x0F00
#define HSHK_CFG_OFFSET 0x001F
#define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
#define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
#define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
#define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
#define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
#define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
#define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
#define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
#define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
#define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
#define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
#define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
#define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
#define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
/*
* Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
* ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
*/
#define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
#define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
/*
* All fields here are accessed by the board microcode and need to be
* little-endian.
*/
typedef struct adv_carr_t {
__le32 carr_va; /* Carrier Virtual Address */
__le32 carr_pa; /* Carrier Physical Address */
__le32 areq_vpa; /* ADV_SCSI_REQ_Q Virtual or Physical Address */
/*
* next_vpa [31:4] Carrier Virtual or Physical Next Pointer
*
* next_vpa [3:1] Reserved Bits
* next_vpa [0] Done Flag set in Response Queue.
*/
__le32 next_vpa;
} ADV_CARR_T;
/*
* Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
*/
#define ADV_NEXT_VPA_MASK 0xFFFFFFF0
#define ADV_RQ_DONE 0x00000001
#define ADV_RQ_GOOD 0x00000002
#define ADV_CQ_STOPPER 0x00000000
#define ADV_GET_CARRP(carrp) ((carrp) & ADV_NEXT_VPA_MASK)
/*
* Each carrier is 64 bytes, and we need three additional
* carrier for icq, irq, and the termination carrier.
*/
#define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 3)
#define ADV_CARRIER_BUFSIZE \
(ADV_CARRIER_COUNT * sizeof(ADV_CARR_T))
#define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
#define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
#define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
/*
* Adapter temporary configuration structure
*
* This structure can be discarded after initialization. Don't add
* fields here needed after initialization.
*
* Field naming convention:
*
* *_enable indicates the field enables or disables a feature. The
* value of the field is never reset.
*/
typedef struct adv_dvc_cfg {
ushort disc_enable; /* enable disconnection */
uchar chip_version; /* chip version */
uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
ushort control_flag; /* Microcode Control Flag */
ushort mcode_date; /* Microcode date */
ushort mcode_version; /* Microcode version */
ushort serial1; /* EEPROM serial number word 1 */
ushort serial2; /* EEPROM serial number word 2 */
ushort serial3; /* EEPROM serial number word 3 */
} ADV_DVC_CFG;
struct adv_dvc_var;
struct adv_scsi_req_q;
typedef struct adv_sg_block {
uchar reserved1;
uchar reserved2;
uchar reserved3;
uchar sg_cnt; /* Valid entries in block. */
__le32 sg_ptr; /* Pointer to next sg block. */
struct {
__le32 sg_addr; /* SG element address. */
__le32 sg_count; /* SG element count. */
} sg_list[NO_OF_SG_PER_BLOCK];
} ADV_SG_BLOCK;
/*
* ADV_SCSI_REQ_Q - microcode request structure
*
* All fields in this structure up to byte 60 are used by the microcode.
* The microcode makes assumptions about the size and ordering of fields
* in this structure. Do not change the structure definition here without
* coordinating the change with the microcode.
*
* All fields accessed by microcode must be maintained in little_endian
* order.
*/
typedef struct adv_scsi_req_q {
uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
uchar target_cmd;
uchar target_id; /* Device target identifier. */
uchar target_lun; /* Device target logical unit number. */
__le32 data_addr; /* Data buffer physical address. */
__le32 data_cnt; /* Data count. Ucode sets to residual. */
__le32 sense_addr;
__le32 carr_pa;
uchar mflag;
uchar sense_len;
uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
uchar scsi_cntl;
uchar done_status; /* Completion status. */
uchar scsi_status; /* SCSI status byte. */
uchar host_status; /* Ucode host status. */
uchar sg_working_ix;
uchar cdb[12]; /* SCSI CDB bytes 0-11. */
__le32 sg_real_addr; /* SG list physical address. */
__le32 scsiq_rptr;
uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
__le32 scsiq_ptr;
__le32 carr_va;
/*
* End of microcode structure - 60 bytes. The rest of the structure
* is used by the Adv Library and ignored by the microcode.
*/
u32 srb_tag;
ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
} ADV_SCSI_REQ_Q;
/*
* The following two structures are used to process Wide Board requests.
*
* The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
* and microcode with the ADV_SCSI_REQ_Q field 'srb_tag' set to the
* SCSI request tag. The adv_req_t structure 'cmndp' field in turn points
* to the Mid-Level SCSI request structure.
*
* Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
* ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
* up to 255 scatter-gather elements may be used per request or
* ADV_SCSI_REQ_Q.
*
* Both structures must be 32 byte aligned.
*/
typedef struct adv_sgblk {
ADV_SG_BLOCK sg_block; /* Sgblock structure. */
dma_addr_t sg_addr; /* Physical address */
struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
} adv_sgblk_t;
typedef struct adv_req {
ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
uchar align[24]; /* Request structure padding. */
struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
dma_addr_t req_addr;
adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
} adv_req_t __aligned(32);
/*
* Adapter operation variable structure.
*
* One structure is required per host adapter.
*
* Field naming convention:
*
* *_able indicates both whether a feature should be enabled or disabled
* and whether a device isi capable of the feature. At initialization
* this field may be set, but later if a device is found to be incapable
* of the feature, the field is cleared.
*/
typedef struct adv_dvc_var {
AdvPortAddr iop_base; /* I/O port address */
ushort err_code; /* fatal error code */
ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
ushort wdtr_able; /* try WDTR for a device */
ushort sdtr_able; /* try SDTR for a device */
ushort ultra_able; /* try SDTR Ultra speed for a device */
ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
ushort tagqng_able; /* try tagged queuing with a device */
ushort ppr_able; /* PPR message capable per TID bitmask. */
uchar max_dvc_qng; /* maximum number of tagged commands per device */
ushort start_motor; /* start motor command allowed */
uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
uchar chip_no; /* should be assigned by caller */
uchar max_host_qng; /* maximum number of Q'ed command allowed */
ushort no_scam; /* scam_tolerant of EEPROM */
struct asc_board *drv_ptr; /* driver pointer to private structure */
uchar chip_scsi_id; /* chip SCSI target ID */
uchar chip_type;
uchar bist_err_code;
ADV_CARR_T *carrier;
ADV_CARR_T *carr_freelist; /* Carrier free list. */
dma_addr_t carrier_addr;
ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
ushort carr_pending_cnt; /* Count of pending carriers. */
/*
* Note: The following fields will not be used after initialization. The
* driver may discard the buffer after initialization is done.
*/
ADV_DVC_CFG *cfg; /* temporary configuration structure */
} ADV_DVC_VAR;
/*
* Microcode idle loop commands
*/
#define IDLE_CMD_COMPLETED 0
#define IDLE_CMD_STOP_CHIP 0x0001
#define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
#define IDLE_CMD_SEND_INT 0x0004
#define IDLE_CMD_ABORT 0x0008
#define IDLE_CMD_DEVICE_RESET 0x0010
#define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
#define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
#define IDLE_CMD_SCSIREQ 0x0080
#define IDLE_CMD_STATUS_SUCCESS 0x0001
#define IDLE_CMD_STATUS_FAILURE 0x0002
/*
* AdvSendIdleCmd() flag definitions.
*/
#define ADV_NOWAIT 0x01
/*
* Wait loop time out values.
*/
#define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
#define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
#define SCSI_MAX_RETRY 10 /* retry count */
#define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
#define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
#define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
#define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
#define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
/* Read byte from a register. */
#define AdvReadByteRegister(iop_base, reg_off) \
(ADV_MEM_READB((iop_base) + (reg_off)))
/* Write byte to a register. */
#define AdvWriteByteRegister(iop_base, reg_off, byte) \
(ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
/* Read word (2 bytes) from a register. */
#define AdvReadWordRegister(iop_base, reg_off) \
(ADV_MEM_READW((iop_base) + (reg_off)))
/* Write word (2 bytes) to a register. */
#define AdvWriteWordRegister(iop_base, reg_off, word) \
(ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
/* Write dword (4 bytes) to a register. */
#define AdvWriteDWordRegister(iop_base, reg_off, dword) \
(ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
/* Read byte from LRAM. */
#define AdvReadByteLram(iop_base, addr, byte) \
do { \
ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
(byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
} while (0)
/* Write byte to LRAM. */
#define AdvWriteByteLram(iop_base, addr, byte) \
(ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
/* Read word (2 bytes) from LRAM. */
#define AdvReadWordLram(iop_base, addr, word) \
do { \
ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
(word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
} while (0)
/* Write word (2 bytes) to LRAM. */
#define AdvWriteWordLram(iop_base, addr, word) \
(ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
/* Write little-endian double word (4 bytes) to LRAM */
/* Because of unspecified C language ordering don't use auto-increment. */
#define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
(ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
/* Read word (2 bytes) from LRAM assuming that the address is already set. */
#define AdvReadWordAutoIncLram(iop_base) \
(ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
/* Write word (2 bytes) to LRAM assuming that the address is already set. */
#define AdvWriteWordAutoIncLram(iop_base, word) \
(ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
/*
* Define macro to check for Condor signature.
*
* Evaluate to ADV_TRUE if a Condor chip is found the specified port
* address 'iop_base'. Otherwise evalue to ADV_FALSE.
*/
#define AdvFindSignature(iop_base) \
(((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
ADV_CHIP_ID_BYTE) && \
(AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
/*
* Define macro to Return the version number of the chip at 'iop_base'.
*
* The second parameter 'bus_type' is currently unused.
*/
#define AdvGetChipVersion(iop_base, bus_type) \
AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
/*
* Abort an SRB in the chip's RISC Memory. The 'srb_tag' argument must
* match the ADV_SCSI_REQ_Q 'srb_tag' field.
*
* If the request has not yet been sent to the device it will simply be
* aborted from RISC memory. If the request is disconnected it will be
* aborted on reselection by sending an Abort Message to the target ID.
*
* Return value:
* ADV_TRUE(1) - Queue was successfully aborted.
* ADV_FALSE(0) - Queue was not found on the active queue list.
*/
#define AdvAbortQueue(asc_dvc, srb_tag) \
AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
(ADV_DCNT) (srb_tag))
/*
* Send a Bus Device Reset Message to the specified target ID.
*
* All outstanding commands will be purged if sending the
* Bus Device Reset Message is successful.
*
* Return Value:
* ADV_TRUE(1) - All requests on the target are purged.
* ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
* are not purged.
*/
#define AdvResetDevice(asc_dvc, target_id) \
AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
(ADV_DCNT) (target_id))
/*
* SCSI Wide Type definition.
*/
#define ADV_SCSI_BIT_ID_TYPE ushort
/*
* AdvInitScsiTarget() 'cntl_flag' options.
*/
#define ADV_SCAN_LUN 0x01
#define ADV_CAPINFO_NOLUN 0x02
/*
* Convert target id to target id bit mask.
*/
#define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
/*
* ADV_SCSI_REQ_Q 'done_status' and 'host_status' return values.
*/
#define QD_NO_STATUS 0x00 /* Request not completed yet. */
#define QD_NO_ERROR 0x01
#define QD_ABORTED_BY_HOST 0x02
#define QD_WITH_ERROR 0x04
#define QHSTA_NO_ERROR 0x00
#define QHSTA_M_SEL_TIMEOUT 0x11
#define QHSTA_M_DATA_OVER_RUN 0x12
#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
#define QHSTA_M_QUEUE_ABORTED 0x15
#define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
#define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
#define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
#define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
#define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
#define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
#define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
/* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
#define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
#define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
#define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
#define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
#define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
#define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
#define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
#define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
#define QHSTA_M_WTM_TIMEOUT 0x41
#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
#define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
#define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
#define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
/* Return the address that is aligned at the next doubleword >= to 'addr'. */
#define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
/*
* Total contiguous memory needed for driver SG blocks.
*
* ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
* number of scatter-gather elements the driver supports in a
* single request.
*/
#define ADV_SG_LIST_MAX_BYTE_SIZE \
(sizeof(ADV_SG_BLOCK) * \
((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
/* struct asc_board flags */
#define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
#define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
#define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
#define ASC_INFO_SIZE 128 /* advansys_info() line size */
/* Asc Library return codes */
#define ASC_TRUE 1
#define ASC_FALSE 0
#define ASC_NOERROR 1
#define ASC_BUSY 0
#define ASC_ERROR (-1)
/* struct scsi_cmnd function return codes */
#define STATUS_BYTE(byte) (byte)
#define MSG_BYTE(byte) ((byte) << 8)
#define HOST_BYTE(byte) ((byte) << 16)
#define DRIVER_BYTE(byte) ((byte) << 24)
#define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
#ifndef ADVANSYS_STATS
#define ASC_STATS_ADD(shost, counter, count)
#else /* ADVANSYS_STATS */
#define ASC_STATS_ADD(shost, counter, count) \
(((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
#endif /* ADVANSYS_STATS */
/* If the result wraps when calculating tenths, return 0. */
#define ASC_TENTHS(num, den) \
(((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
/*
* Display a message to the console.
*/
#define ASC_PRINT(s) \
{ \
printk("advansys: "); \
printk(s); \
}
#define ASC_PRINT1(s, a1) \
{ \
printk("advansys: "); \
printk((s), (a1)); \
}
#define ASC_PRINT2(s, a1, a2) \
{ \
printk("advansys: "); \
printk((s), (a1), (a2)); \
}
#define ASC_PRINT3(s, a1, a2, a3) \
{ \
printk("advansys: "); \
printk((s), (a1), (a2), (a3)); \
}
#define ASC_PRINT4(s, a1, a2, a3, a4) \
{ \
printk("advansys: "); \
printk((s), (a1), (a2), (a3), (a4)); \
}
#ifndef ADVANSYS_DEBUG
#define ASC_DBG(lvl, s...)
#define ASC_DBG_PRT_SCSI_HOST(lvl, s)
#define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
#define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
#define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
#define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
#define ASC_DBG_PRT_HEX(lvl, name, start, length)
#define ASC_DBG_PRT_CDB(lvl, cdb, len)
#define ASC_DBG_PRT_SENSE(lvl, sense, len)
#define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
#else /* ADVANSYS_DEBUG */
/*
* Debugging Message Levels:
* 0: Errors Only
* 1: High-Level Tracing
* 2-N: Verbose Tracing
*/
#define ASC_DBG(lvl, format, arg...) { \
if (asc_dbglvl >= (lvl)) \
printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \
__func__ , ## arg); \
}
#define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
{ \
if (asc_dbglvl >= (lvl)) { \
asc_prt_scsi_host(s); \
} \
}
#define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
{ \
if (asc_dbglvl >= (lvl)) { \
asc_prt_asc_scsi_q(scsiqp); \
} \
}
#define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
{ \
if (asc_dbglvl >= (lvl)) { \
asc_prt_asc_qdone_info(qdone); \
} \
}
#define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
{ \
if (asc_dbglvl >= (lvl)) { \
asc_prt_adv_scsi_req_q(scsiqp); \
} \
}
#define ASC_DBG_PRT_HEX(lvl, name, start, length) \
{ \
if (asc_dbglvl >= (lvl)) { \
asc_prt_hex((name), (start), (length)); \
} \
}
#define ASC_DBG_PRT_CDB(lvl, cdb, len) \
ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
#define ASC_DBG_PRT_SENSE(lvl, sense, len) \
ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
#define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
#endif /* ADVANSYS_DEBUG */
#ifdef ADVANSYS_STATS
/* Per board statistics structure */
struct asc_stats {
/* Driver Entrypoint Statistics */
unsigned int queuecommand; /* # calls to advansys_queuecommand() */
unsigned int reset; /* # calls to advansys_eh_bus_reset() */
unsigned int biosparam; /* # calls to advansys_biosparam() */
unsigned int interrupt; /* # advansys_interrupt() calls */
unsigned int callback; /* # calls to asc/adv_isr_callback() */
unsigned int done; /* # calls to request's scsi_done function */
unsigned int build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
unsigned int adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
unsigned int adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
/* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
unsigned int exe_noerror; /* # ASC_NOERROR returns. */
unsigned int exe_busy; /* # ASC_BUSY returns. */
unsigned int exe_error; /* # ASC_ERROR returns. */
unsigned int exe_unknown; /* # unknown returns. */
/* Data Transfer Statistics */
unsigned int xfer_cnt; /* # I/O requests received */
unsigned int xfer_elem; /* # scatter-gather elements */
unsigned int xfer_sect; /* # 512-byte blocks */
};
#endif /* ADVANSYS_STATS */
/*
* Structure allocated for each board.
*
* This structure is allocated by scsi_host_alloc() at the end
* of the 'Scsi_Host' structure starting at the 'hostdata'
* field. It is guaranteed to be allocated from DMA-able memory.
*/
struct asc_board {
struct device *dev;
struct Scsi_Host *shost;
uint flags; /* Board flags */
unsigned int irq;
union {
ASC_DVC_VAR asc_dvc_var; /* Narrow board */
ADV_DVC_VAR adv_dvc_var; /* Wide board */
} dvc_var;
union {
ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
} dvc_cfg;
ushort asc_n_io_port; /* Number I/O ports. */
ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
union {
ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
} eep_config;
/* /proc/scsi/advansys/[0...] */
#ifdef ADVANSYS_STATS
struct asc_stats asc_stats; /* Board statistics */
#endif /* ADVANSYS_STATS */
/*
* The following fields are used only for Narrow Boards.
*/
uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
/*
* The following fields are used only for Wide Boards.
*/
void __iomem *ioremap_addr; /* I/O Memory remap address. */
ushort ioport; /* I/O Port address. */
adv_req_t *adv_reqp; /* Request structures. */
dma_addr_t adv_reqp_addr;
size_t adv_reqp_size;
struct dma_pool *adv_sgblk_pool; /* Scatter-gather structures. */
ushort bios_signature; /* BIOS Signature. */
ushort bios_version; /* BIOS Version. */
ushort bios_codeseg; /* BIOS Code Segment. */
ushort bios_codelen; /* BIOS Code Segment Length. */
};
#define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
dvc_var.asc_dvc_var)
#define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
dvc_var.adv_dvc_var)
#define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
#ifdef ADVANSYS_DEBUG
static int asc_dbglvl = 3;
/*
* asc_prt_asc_dvc_var()
*/
static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
{
printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
"%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
(unsigned)h->init_sdtr);
printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
"chip_no 0x%x,\n", (unsigned)h->sdtr_done,
(unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
(unsigned)h->chip_no);
printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
"%u,\n", (unsigned)h->queue_full_or_busy,
(unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
"in_critical_cnt %u,\n", (unsigned)h->is_in_int,
(unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
(unsigned)h->in_critical_cnt);
printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
"pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
(unsigned)h->init_state, (unsigned)h->no_scam,
(unsigned)h->pci_fix_asyn_xfer);
printk(" cfg 0x%lx\n", (ulong)h->cfg);
}
/*
* asc_prt_asc_dvc_cfg()
*/
static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
{
printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
h->can_tagged_qng, h->cmd_qng_enabled);
printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
h->disc_enable, h->sdtr_enable);
printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
"chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
h->isa_dma_channel, h->chip_version);
printk(" mcode_date 0x%x, mcode_version %d\n",
h->mcode_date, h->mcode_version);
}
/*
* asc_prt_adv_dvc_var()
*
* Display an ADV_DVC_VAR structure.
*/
static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
{
printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
(ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
printk(" sdtr_able 0x%x, wdtr_able 0x%x\n",
(unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n",
(unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%p\n",
(unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
h->carr_freelist);
printk(" icq_sp 0x%p, irq_sp 0x%p\n", h->icq_sp, h->irq_sp);
printk(" no_scam 0x%x, tagqng_able 0x%x\n",
(unsigned)h->no_scam, (unsigned)h->tagqng_able);
printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
(unsigned)h->chip_scsi_id, (ulong)h->cfg);
}
/*
* asc_prt_adv_dvc_cfg()
*
* Display an ADV_DVC_CFG structure.
*/
static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
{
printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
printk(" disc_enable 0x%x, termination 0x%x\n",
h->disc_enable, h->termination);
printk(" chip_version 0x%x, mcode_date 0x%x\n",
h->chip_version, h->mcode_date);
printk(" mcode_version 0x%x, control_flag 0x%x\n",
h->mcode_version, h->control_flag);
}
/*
* asc_prt_scsi_host()
*/
static void asc_prt_scsi_host(struct Scsi_Host *s)
{
struct asc_board *boardp = shost_priv(s);
printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
printk(" host_busy %u, host_no %d,\n",
atomic_read(&s->host_busy), s->host_no);
printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
(ulong)s->base, (ulong)s->io_port, boardp->irq);
printk(" dma_channel %d, this_id %d, can_queue %d,\n",
s->dma_channel, s->this_id, s->can_queue);
printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
if (ASC_NARROW_BOARD(boardp)) {
asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
} else {
asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
}
}
/*
* asc_prt_hex()
*
* Print hexadecimal output in 4 byte groupings 32 bytes
* or 8 double-words per line.
*/
static void asc_prt_hex(char *f, uchar *s, int l)
{
int i;
int j;
int k;
int m;
printk("%s: (%d bytes)\n", f, l);
for (i = 0; i < l; i += 32) {
/* Display a maximum of 8 double-words per line. */
if ((k = (l - i) / 4) >= 8) {
k = 8;
m = 0;
} else {
m = (l - i) % 4;
}
for (j = 0; j < k; j++) {
printk(" %2.2X%2.2X%2.2X%2.2X",
(unsigned)s[i + (j * 4)],
(unsigned)s[i + (j * 4) + 1],
(unsigned)s[i + (j * 4) + 2],
(unsigned)s[i + (j * 4) + 3]);
}
switch (m) {
case 0:
default:
break;
case 1:
printk(" %2.2X", (unsigned)s[i + (j * 4)]);
break;
case 2:
printk(" %2.2X%2.2X",
(unsigned)s[i + (j * 4)],
(unsigned)s[i + (j * 4) + 1]);
break;
case 3:
printk(" %2.2X%2.2X%2.2X",
(unsigned)s[i + (j * 4) + 1],
(unsigned)s[i + (j * 4) + 2],
(unsigned)s[i + (j * 4) + 3]);
break;
}
printk("\n");
}
}
/*
* asc_prt_asc_scsi_q()
*/
static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
{
ASC_SG_HEAD *sgp;
int i;
printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
printk
(" target_ix 0x%x, target_lun %u, srb_tag 0x%x, tag_code 0x%x,\n",
q->q2.target_ix, q->q1.target_lun, q->q2.srb_tag,
q->q2.tag_code);
printk
(" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
(ulong)le32_to_cpu(q->q1.data_addr),
(ulong)le32_to_cpu(q->q1.data_cnt),
(ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
(ulong)q->cdbptr, q->q2.cdb_len,
(ulong)q->sg_head, q->q1.sg_queue_cnt);
if (q->sg_head) {
sgp = q->sg_head;
printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
sgp->queue_cnt);
for (i = 0; i < sgp->entry_cnt; i++) {
printk(" [%u]: addr 0x%lx, bytes %lu\n",
i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
(ulong)le32_to_cpu(sgp->sg_list[i].bytes));
}
}
}
/*
* asc_prt_asc_qdone_info()
*/
static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
{
printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
printk(" srb_tag 0x%x, target_ix %u, cdb_len %u, tag_code %u,\n",
q->d2.srb_tag, q->d2.target_ix, q->d2.cdb_len,
q->d2.tag_code);
printk
(" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
}
/*
* asc_prt_adv_sgblock()
*
* Display an ADV_SG_BLOCK structure.
*/
static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
{
int i;
printk(" ADV_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
(ulong)b, sgblockno);
printk(" sg_cnt %u, sg_ptr 0x%x\n",
b->sg_cnt, (u32)le32_to_cpu(b->sg_ptr));
BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
if (b->sg_ptr != 0)
BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
for (i = 0; i < b->sg_cnt; i++) {
printk(" [%u]: sg_addr 0x%x, sg_count 0x%x\n",
i, (u32)le32_to_cpu(b->sg_list[i].sg_addr),
(u32)le32_to_cpu(b->sg_list[i].sg_count));
}
}
/*
* asc_prt_adv_scsi_req_q()
*
* Display an ADV_SCSI_REQ_Q structure.
*/
static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
{
int sg_blk_cnt;
struct adv_sg_block *sg_ptr;
adv_sgblk_t *sgblkp;
printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
printk(" target_id %u, target_lun %u, srb_tag 0x%x\n",
q->target_id, q->target_lun, q->srb_tag);
printk(" cntl 0x%x, data_addr 0x%lx\n",
q->cntl, (ulong)le32_to_cpu(q->data_addr));
printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
(ulong)le32_to_cpu(q->data_cnt),
(ulong)le32_to_cpu(q->sense_addr), q->sense_len);
printk
(" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
q->cdb_len, q->done_status, q->host_status, q->scsi_status);
printk(" sg_working_ix 0x%x, target_cmd %u\n",
q->sg_working_ix, q->target_cmd);
printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
(ulong)le32_to_cpu(q->scsiq_rptr),
(ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
/* Display the request's ADV_SG_BLOCK structures. */
if (q->sg_list_ptr != NULL) {
sgblkp = container_of(q->sg_list_ptr, adv_sgblk_t, sg_block);
sg_blk_cnt = 0;
while (sgblkp) {
sg_ptr = &sgblkp->sg_block;
asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
if (sg_ptr->sg_ptr == 0) {
break;
}
sgblkp = sgblkp->next_sgblkp;
sg_blk_cnt++;
}
}
}
#endif /* ADVANSYS_DEBUG */
/*
* advansys_info()
*
* Return suitable for printing on the console with the argument
* adapter's configuration information.
*
* Note: The information line should not exceed ASC_INFO_SIZE bytes,
* otherwise the static 'info' array will be overrun.
*/
static const char *advansys_info(struct Scsi_Host *shost)
{
static char info[ASC_INFO_SIZE];
struct asc_board *boardp = shost_priv(shost);
ASC_DVC_VAR *asc_dvc_varp;
ADV_DVC_VAR *adv_dvc_varp;
char *busname;
char *widename = NULL;
if (ASC_NARROW_BOARD(boardp)) {
asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
ASC_DBG(1, "begin\n");
if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
ASC_IS_ISAPNP) {
busname = "ISA PnP";
} else {
busname = "ISA";
}
sprintf(info,
"AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
ASC_VERSION, busname,
(ulong)shost->io_port,
(ulong)shost->io_port + ASC_IOADR_GAP - 1,
boardp->irq, shost->dma_channel);
} else {
if (asc_dvc_varp->bus_type & ASC_IS_VL) {
busname = "VL";
} else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
busname = "EISA";
} else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
== ASC_IS_PCI_ULTRA) {
busname = "PCI Ultra";
} else {
busname = "PCI";
}
} else {
busname = "?";
shost_printk(KERN_ERR, shost, "unknown bus "
"type %d\n", asc_dvc_varp->bus_type);
}
sprintf(info,
"AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
ASC_VERSION, busname, (ulong)shost->io_port,
(ulong)shost->io_port + ASC_IOADR_GAP - 1,
boardp->irq);
}
} else {
/*
* Wide Adapter Information
*
* Memory-mapped I/O is used instead of I/O space to access
* the adapter, but display the I/O Port range. The Memory
* I/O address is displayed through the driver /proc file.
*/
adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
widename = "Ultra-Wide";
} else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
widename = "Ultra2-Wide";
} else {
widename = "Ultra3-Wide";
}
sprintf(info,
"AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
(ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
}
BUG_ON(strlen(info) >= ASC_INFO_SIZE);
ASC_DBG(1, "end\n");
return info;
}
#ifdef CONFIG_PROC_FS
/*
* asc_prt_board_devices()
*
* Print driver information for devices attached to the board.
*/
static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost)
{
struct asc_board *boardp = shost_priv(shost);
int chip_scsi_id;
int i;
seq_printf(m,
"\nDevice Information for AdvanSys SCSI Host %d:\n",
shost->host_no);
if (ASC_NARROW_BOARD(boardp)) {
chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
} else {
chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
}
seq_puts(m, "Target IDs Detected:");
for (i = 0; i <= ADV_MAX_TID; i++) {
if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i))
seq_printf(m, " %X,", i);
}
seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id);
}
/*
* Display Wide Board BIOS Information.
*/
static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost)
{
struct asc_board *boardp = shost_priv(shost);
ushort major, minor, letter;
seq_puts(m, "\nROM BIOS Version: ");
/*
* If the BIOS saved a valid signature, then fill in
* the BIOS code segment base address.
*/
if (boardp->bios_signature != 0x55AA) {
seq_puts(m, "Disabled or Pre-3.1\n"
"BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n"
"can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
} else {
major = (boardp->bios_version >> 12) & 0xF;
minor = (boardp->bios_version >> 8) & 0xF;
letter = (boardp->bios_version & 0xFF);
seq_printf(m, "%d.%d%c\n",
major, minor,
letter >= 26 ? '?' : letter + 'A');
/*
* Current available ROM BIOS release is 3.1I for UW
* and 3.2I for U2W. This code doesn't differentiate
* UW and U2W boards.
*/
if (major < 3 || (major <= 3 && minor < 1) ||
(major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
seq_puts(m, "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n"
"ftp://ftp.connectcom.net/pub\n");
}
}
}
/*
* Add serial number to information bar if signature AAh
* is found in at bit 15-9 (7 bits) of word 1.
*
* Serial Number consists fo 12 alpha-numeric digits.
*
* 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
* 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
* 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
* 5 - Product revision (A-J) Word0: " "
*
* Signature Word1: 15-9 (7 bits)
* 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
* 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
*
* 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
*
* Note 1: Only production cards will have a serial number.
*
* Note 2: Signature is most significant 7 bits (0xFE).
*
* Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
*/
static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
{
ushort w, num;
if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
return ASC_FALSE;
} else {
/*
* First word - 6 digits.
*/
w = serialnum[0];
/* Product type - 1st digit. */
if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
/* Product type is P=Prototype */
*cp += 0x8;
}
cp++;
/* Manufacturing location - 2nd digit. */
*cp++ = 'A' + ((w & 0x1C00) >> 10);
/* Product ID - 3rd, 4th digits. */
num = w & 0x3FF;
*cp++ = '0' + (num / 100);
num %= 100;
*cp++ = '0' + (num / 10);
/* Product revision - 5th digit. */
*cp++ = 'A' + (num % 10);
/*
* Second word
*/
w = serialnum[1];
/*
* Year - 6th digit.
*
* If bit 15 of third word is set, then the
* last digit of the year is greater than 7.
*/
if (serialnum[2] & 0x8000) {
*cp++ = '8' + ((w & 0x1C0) >> 6);
} else {
*cp++ = '0' + ((w & 0x1C0) >> 6);
}
/* Week of year - 7th, 8th digits. */
num = w & 0x003F;
*cp++ = '0' + num / 10;
num %= 10;
*cp++ = '0' + num;
/*
* Third word
*/
w = serialnum[2] & 0x7FFF;
/* Serial number - 9th digit. */
*cp++ = 'A' + (w / 1000);
/* 10th, 11th, 12th digits. */
num = w % 1000;
*cp++ = '0' + num / 100;
num %= 100;
*cp++ = '0' + num / 10;
num %= 10;
*cp++ = '0' + num;
*cp = '\0'; /* Null Terminate the string. */
return ASC_TRUE;
}
}
/*
* asc_prt_asc_board_eeprom()
*
* Print board EEPROM configuration.
*/
static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
{
struct asc_board *boardp = shost_priv(shost);
ASC_DVC_VAR *asc_dvc_varp;
ASCEEP_CONFIG *ep;
int i;
#ifdef CONFIG_ISA
int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
#endif /* CONFIG_ISA */
uchar serialstr[13];
asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
ep = &boardp->eep_config.asc_eep;
seq_printf(m,
"\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
shost->host_no);
if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
== ASC_TRUE)
seq_printf(m, " Serial Number: %s\n", serialstr);
else if (ep->adapter_info[5] == 0xBB)
seq_puts(m,
" Default Settings Used for EEPROM-less Adapter.\n");
else
seq_puts(m, " Serial Number Signature Not Present.\n");
seq_printf(m,
" Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
ep->max_tag_qng);
seq_printf(m,
" cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
seq_puts(m, " Target ID: ");
for (i = 0; i <= ASC_MAX_TID; i++)
seq_printf(m, " %d", i);
seq_puts(m, "\n Disconnects: ");
for (i = 0; i <= ASC_MAX_TID; i++)
seq_printf(m, " %c",
(ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
seq_puts(m, "\n Command Queuing: ");
for (i = 0; i <= ASC_MAX_TID; i++)
seq_printf(m, " %c",
(ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
seq_puts(m, "\n Start Motor: ");
for (i = 0; i <= ASC_MAX_TID; i++)
seq_printf(m, " %c",
(ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
seq_puts(m, "\n Synchronous Transfer:");
for (i = 0; i <= ASC_MAX_TID; i++)
seq_printf(m, " %c",
(ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
seq_putc(m, '\n');
#ifdef CONFIG_ISA
if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
seq_printf(m,
" Host ISA DMA speed: %d MB/S\n",
isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
}
#endif /* CONFIG_ISA */
}
/*
* asc_prt_adv_board_eeprom()
*
* Print board EEPROM configuration.
*/
static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
{
struct asc_board *boardp = shost_priv(shost);
ADV_DVC_VAR *adv_dvc_varp;
int i;
char *termstr;
uchar serialstr[13];
ADVEEP_3550_CONFIG *ep_3550 = NULL;
ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
ushort word;
ushort *wordp;
ushort sdtr_speed = 0;
adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
ep_3550 = &boardp->eep_config.adv_3550_eep;
} else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
} else {
ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
}
seq_printf(m,
"\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
shost->host_no);
if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
wordp = &ep_3550->serial_number_word1;
} else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
wordp = &ep_38C0800->serial_number_word1;
} else {
wordp = &ep_38C1600->serial_number_word1;
}
if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE)
seq_printf(m, " Serial Number: %s\n", serialstr);
else
seq_puts(m, " Serial Number Signature Not Present.\n");
if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
seq_printf(m,
" Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
ep_3550->adapter_scsi_id,
ep_3550->max_host_qng, ep_3550->max_dvc_qng);
else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
seq_printf(m,
" Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
ep_38C0800->adapter_scsi_id,
ep_38C0800->max_host_qng,
ep_38C0800->max_dvc_qng);
else
seq_printf(m,
" Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
ep_38C1600->adapter_scsi_id,
ep_38C1600->max_host_qng,
ep_38C1600->max_dvc_qng);
if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
word = ep_3550->termination;
} else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
word = ep_38C0800->termination_lvd;
} else {
word = ep_38C1600->termination_lvd;
}
switch (word) {
case 1:
termstr = "Low Off/High Off";
break;
case 2:
termstr = "Low Off/High On";
break;
case 3:
termstr = "Low On/High On";
break;
default:
case 0:
termstr = "Automatic";
break;
}
if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
seq_printf(m,
" termination: %u (%s), bios_ctrl: 0x%x\n",
ep_3550->termination, termstr,
ep_3550->bios_ctrl);
else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
seq_printf(m,
" termination: %u (%s), bios_ctrl: 0x%x\n",
ep_38C0800->termination_lvd, termstr,
ep_38C0800->bios_ctrl);
else
seq_printf(m,
" termination: %u (%s), bios_ctrl: 0x%x\n",
ep_38C1600->termination_lvd, termstr,
ep_38C1600->bios_ctrl);
seq_puts(m, " Target ID: ");
for (i = 0; i <= ADV_MAX_TID; i++)
seq_printf(m, " %X", i);
seq_putc(m, '\n');
if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
word = ep_3550->disc_enable;
} else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
word = ep_38C0800->disc_enable;
} else {
word = ep_38C1600->disc_enable;
}
seq_puts(m, " Disconnects: ");
for (i = 0; i <= ADV_MAX_TID; i++)
seq_printf(m, " %c",
(word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
seq_putc(m, '\n');
if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
word = ep_3550->tagqng_able;
} else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
word = ep_38C0800->tagqng_able;
} else {
word = ep_38C1600->tagqng_able;
}
seq_puts(m, " Command Queuing: ");
for (i = 0; i <= ADV_MAX_TID; i++)
seq_printf(m, " %c",
(word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
seq_putc(m, '\n');
if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
word = ep_3550->start_motor;
} else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
word = ep_38C0800->start_motor;
} else {
word = ep_38C1600->start_motor;
}
seq_puts(m, " Start Motor: ");
for (i = 0; i <= ADV_MAX_TID; i++)
seq_printf(m, " %c",
(word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
seq_putc(m, '\n');
if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
seq_puts(m, " Synchronous Transfer:");
for (i = 0; i <= ADV_MAX_TID; i++)
seq_printf(m, " %c",
(ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
'Y' : 'N');
seq_putc(m, '\n');
}
if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
seq_puts(m, " Ultra Transfer: ");
for (i = 0; i <= ADV_MAX_TID; i++)
seq_printf(m, " %c",
(ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i))
? 'Y' : 'N');
seq_putc(m, '\n');
}
if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
word = ep_3550->wdtr_able;
} else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
word = ep_38C0800->wdtr_able;
} else {
word = ep_38C1600->wdtr_able;
}
seq_puts(m, " Wide Transfer: ");
for (i = 0; i <= ADV_MAX_TID; i++)
seq_printf(m, " %c",
(word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
seq_putc(m, '\n');
if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
seq_puts(m, " Synchronous Transfer Speed (Mhz):\n ");
for (i = 0; i <= ADV_MAX_TID; i++) {
char *speed_str;
if (i == 0) {
sdtr_speed = adv_dvc_varp->sdtr_speed1;
} else if (i == 4) {
sdtr_speed = adv_dvc_varp->sdtr_speed2;
} else if (i == 8) {
sdtr_speed = adv_dvc_varp->sdtr_speed3;
} else if (i == 12) {
sdtr_speed = adv_dvc_varp->sdtr_speed4;
}
switch (sdtr_speed & ADV_MAX_TID) {
case 0:
speed_str = "Off";
break;
case 1:
speed_str = " 5";
break;
case 2:
speed_str = " 10";
break;
case 3:
speed_str = " 20";
break;
case 4:
speed_str = " 40";
break;
case 5:
speed_str = " 80";
break;
default:
speed_str = "Unk";
break;
}
seq_printf(m, "%X:%s ", i, speed_str);
if (i == 7)
seq_puts(m, "\n ");
sdtr_speed >>= 4;
}
seq_putc(m, '\n');
}
}
/*
* asc_prt_driver_conf()
*/
static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost)
{
struct asc_board *boardp = shost_priv(shost);
int chip_scsi_id;
seq_printf(m,
"\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
shost->host_no);
seq_printf(m,
" host_busy %u, max_id %u, max_lun %llu, max_channel %u\n",
atomic_read(&shost->host_busy), shost->max_id,
shost->max_lun, shost->max_channel);
seq_printf(m,
" unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
shost->unique_id, shost->can_queue, shost->this_id,
shost->sg_tablesize, shost->cmd_per_lun);
seq_printf(m,
" unchecked_isa_dma %d, use_clustering %d\n",
shost->unchecked_isa_dma, shost->use_clustering);
seq_printf(m,
" flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n",
boardp->flags, shost->last_reset, jiffies,
boardp->asc_n_io_port);
seq_printf(m, " io_port 0x%lx\n", shost->io_port);
if (ASC_NARROW_BOARD(boardp)) {
chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
} else {
chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
}
}
/*
* asc_prt_asc_board_info()
*
* Print dynamic board configuration information.
*/
static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost)
{
struct asc_board *boardp = shost_priv(shost);
int chip_scsi_id;
ASC_DVC_VAR *v;
ASC_DVC_CFG *c;
int i;
int renegotiate = 0;
v = &boardp->dvc_var.asc_dvc_var;
c = &boardp->dvc_cfg.asc_dvc_cfg;
chip_scsi_id = c->chip_scsi_id;
seq_printf(m,
"\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
shost->host_no);
seq_printf(m, " chip_version %u, mcode_date 0x%x, "
"mcode_version 0x%x, err_code %u\n",
c->chip_version, c->mcode_date, c->mcode_version,
v->err_code);
/* Current number of commands waiting for the host. */
seq_printf(m,
" Total Command Pending: %d\n", v->cur_total_qng);
seq_puts(m, " Command Queuing:");
for (i = 0; i <= ASC_MAX_TID; i++) {
if ((chip_scsi_id == i) ||
((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
continue;
}
seq_printf(m, " %X:%c",
i,
(v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
}
/* Current number of commands waiting for a device. */
seq_puts(m, "\n Command Queue Pending:");
for (i = 0; i <= ASC_MAX_TID; i++) {
if ((chip_scsi_id == i) ||
((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
continue;
}
seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]);
}
/* Current limit on number of commands that can be sent to a device. */
seq_puts(m, "\n Command Queue Limit:");
for (i = 0; i <= ASC_MAX_TID; i++) {
if ((chip_scsi_id == i) ||
((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
continue;
}
seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]);
}
/* Indicate whether the device has returned queue full status. */
seq_puts(m, "\n Command Queue Full:");
for (i = 0; i <= ASC_MAX_TID; i++) {
if ((chip_scsi_id == i) ||
((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
continue;
}
if (boardp->queue_full & ADV_TID_TO_TIDMASK(i))
seq_printf(m, " %X:Y-%d",
i, boardp->queue_full_cnt[i]);
else
seq_printf(m, " %X:N", i);
}
seq_puts(m, "\n Synchronous Transfer:");
for (i = 0; i <= ASC_MAX_TID; i++) {
if ((chip_scsi_id == i) ||
((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
continue;
}
seq_printf(m, " %X:%c",
i,
(v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
}
seq_putc(m, '\n');
for (i = 0; i <= ASC_MAX_TID; i++) {
uchar syn_period_ix;
if ((chip_scsi_id == i) ||
((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
continue;
}
seq_printf(m, " %X:", i);
if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
seq_puts(m, " Asynchronous");
} else {
syn_period_ix =
(boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
1);
seq_printf(m,
" Transfer Period Factor: %d (%d.%d Mhz),",
v->sdtr_period_tbl[syn_period_ix],
250 / v->sdtr_period_tbl[syn_period_ix],
ASC_TENTHS(250,
v->sdtr_period_tbl[syn_period_ix]));
seq_printf(m, " REQ/ACK Offset: %d",
boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
}
if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
seq_puts(m, "*\n");
renegotiate = 1;
} else {
seq_putc(m, '\n');
}
}
if (renegotiate) {
seq_puts(m, " * = Re-negotiation pending before next command.\n");
}
}
/*
* asc_prt_adv_board_info()
*
* Print dynamic board configuration information.
*/
static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost)
{
struct asc_board *boardp = shost_priv(shost);
int i;
ADV_DVC_VAR *v;
ADV_DVC_CFG *c;
AdvPortAddr iop_base;
ushort chip_scsi_id;
ushort lramword;
uchar lrambyte;
ushort tagqng_able;
ushort sdtr_able, wdtr_able;
ushort wdtr_done, sdtr_done;
ushort period = 0;
int renegotiate = 0;
v = &boardp->dvc_var.adv_dvc_var;
c = &boardp->dvc_cfg.adv_dvc_cfg;
iop_base = v->iop_base;
chip_scsi_id = v->chip_scsi_id;
seq_printf(m,
"\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
shost->host_no);
seq_printf(m,
" iop_base 0x%lx, cable_detect: %X, err_code %u\n",
(unsigned long)v->iop_base,
AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT,
v->err_code);
seq_printf(m, " chip_version %u, mcode_date 0x%x, "
"mcode_version 0x%x\n", c->chip_version,
c->mcode_date, c->mcode_version);
AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
seq_puts(m, " Queuing Enabled:");
for (i = 0; i <= ADV_MAX_TID; i++) {
if ((chip_scsi_id == i) ||
((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
continue;
}
seq_printf(m, " %X:%c",
i,
(tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
}
seq_puts(m, "\n Queue Limit:");
for (i = 0; i <= ADV_MAX_TID; i++) {
if ((chip_scsi_id == i) ||
((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
continue;
}
AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
lrambyte);
seq_printf(m, " %X:%d", i, lrambyte);
}
seq_puts(m, "\n Command Pending:");
for (i = 0; i <= ADV_MAX_TID; i++) {
if ((chip_scsi_id == i) ||
((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
continue;
}
AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
lrambyte);
seq_printf(m, " %X:%d", i, lrambyte);
}
seq_putc(m, '\n');
AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
seq_puts(m, " Wide Enabled:");
for (i = 0; i <= ADV_MAX_TID; i++) {
if ((chip_scsi_id == i) ||
((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
continue;
}
seq_printf(m, " %X:%c",
i,
(wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
}
seq_putc(m, '\n');
AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
seq_puts(m, " Transfer Bit Width:");
for (i = 0; i <= ADV_MAX_TID; i++) {
if ((chip_scsi_id == i) ||
((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
continue;
}
AdvReadWordLram(iop_base,
ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
lramword);
seq_printf(m, " %X:%d",
i, (lramword & 0x8000) ? 16 : 8);
if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
(wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
seq_putc(m, '*');
renegotiate = 1;
}
}
seq_putc(m, '\n');
AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
seq_puts(m, " Synchronous Enabled:");
for (i = 0; i <= ADV_MAX_TID; i++) {
if ((chip_scsi_id == i) ||
((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
continue;
}
seq_printf(m, " %X:%c",
i,
(sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
}
seq_putc(m, '\n');
AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
for (i = 0; i <= ADV_MAX_TID; i++) {
AdvReadWordLram(iop_base,
ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
lramword);
lramword &= ~0x8000;
if ((chip_scsi_id == i) ||
((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
continue;
}
seq_printf(m, " %X:", i);
if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
seq_puts(m, " Asynchronous");
} else {
seq_puts(m, " Transfer Period Factor: ");
if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
seq_puts(m, "9 (80.0 Mhz),");
} else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
seq_puts(m, "10 (40.0 Mhz),");
} else { /* 20 Mhz or below. */
period = (((lramword >> 8) * 25) + 50) / 4;
if (period == 0) { /* Should never happen. */