From 09ec417b0ea8bdab18e78d3d55e0a5fb7d54f18c Mon Sep 17 00:00:00 2001 From: Ladislav Michl Date: Tue, 9 Jan 2018 14:19:11 +0100 Subject: [PATCH] mtd: nand: samsung: Disable subpage writes on E-die NAND Samsung E-die SLC NAND manufactured using 21nm process (K9F1G08U0E) does not support partial page programming, so disable subpage writes for it. Manufacturing process is stored in lowest two bits of 5th ID byte. Signed-off-by: Ladislav Michl Signed-off-by: Boris Brezillon --- drivers/mtd/nand/nand_samsung.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/nand_samsung.c b/drivers/mtd/nand/nand_samsung.c index f6b0a63a068c74..ef022f62f74c18 100644 --- a/drivers/mtd/nand/nand_samsung.c +++ b/drivers/mtd/nand/nand_samsung.c @@ -92,10 +92,23 @@ static void samsung_nand_decode_id(struct nand_chip *chip) } else { nand_decode_ext_id(chip); - /* Datasheet values for SLC Samsung K9F4G08U0D-S[I|C]B0(T00) */ - if (nand_is_slc(chip) && chip->id.data[1] == 0xDC) { - chip->ecc_step_ds = 512; - chip->ecc_strength_ds = 1; + if (nand_is_slc(chip)) { + switch (chip->id.data[1]) { + /* K9F4G08U0D-S[I|C]B0(T00) */ + case 0xDC: + chip->ecc_step_ds = 512; + chip->ecc_strength_ds = 1; + break; + + /* K9F1G08U0E 21nm chips do not support subpage write */ + case 0xF1: + if (chip->id.len > 4 && + (chip->id.data[4] & GENMASK(1, 0)) == 0x1) + chip->options |= NAND_NO_SUBPAGE_WRITE; + break; + default: + break; + } } } }