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bbrezillon
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mtd: spi-nor: Move Micron/ST bits out of core.c
Create a SPI NOR manufacturer driver for Micron/ST chips, and move the Micron/ST definitions outside of core.c. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
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-120
lines changed

4 files changed

+158
-120
lines changed

‎drivers/mtd/spi-nor/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,4 +10,5 @@ spi-nor-objs += gigadevice.o
1010
spi-nor-objs += intel.o
1111
spi-nor-objs += issi.o
1212
spi-nor-objs += macronix.o
13+
spi-nor-objs += micron-st.o
1314
obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o

‎drivers/mtd/spi-nor/core.c

Lines changed: 2 additions & 120 deletions
Original file line numberDiff line numberDiff line change
@@ -399,30 +399,6 @@ int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
399399
return ret;
400400
}
401401

402-
/**
403-
* st_micron_set_4byte_addr_mode() - Set 4-byte address mode for ST and Micron
404-
* flashes.
405-
* @nor: pointer to 'struct spi_nor'.
406-
* @enable: true to enter the 4-byte address mode, false to exit the 4-byte
407-
* address mode.
408-
*
409-
* Return: 0 on success, -errno otherwise.
410-
*/
411-
static int st_micron_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
412-
{
413-
int ret;
414-
415-
ret = spi_nor_write_enable(nor);
416-
if (ret)
417-
return ret;
418-
419-
ret = spi_nor_set_4byte_addr_mode(nor, enable);
420-
if (ret)
421-
return ret;
422-
423-
return spi_nor_write_disable(nor);
424-
}
425-
426402
/**
427403
* spansion_set_4byte_addr_mode() - Set 4-byte address mode for Spansion
428404
* flashes.
@@ -2019,53 +1995,6 @@ int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
20191995
* old entries may be missing 4K flag.
20201996
*/
20211997
static const struct flash_info spi_nor_ids[] = {
2022-
/* Micron <--> ST Micro */
2023-
{ "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
2024-
{ "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
2025-
{ "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
2026-
{ "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
2027-
{ "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
2028-
{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K |
2029-
USE_FSR | SPI_NOR_QUAD_READ) },
2030-
{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K |
2031-
USE_FSR | SPI_NOR_QUAD_READ) },
2032-
{ "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512,
2033-
SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
2034-
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
2035-
{ "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K |
2036-
USE_FSR | SPI_NOR_DUAL_READ |
2037-
SPI_NOR_QUAD_READ) },
2038-
{ "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512,
2039-
SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
2040-
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
2041-
{ "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K |
2042-
USE_FSR | SPI_NOR_QUAD_READ) },
2043-
{ "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024,
2044-
SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
2045-
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
2046-
{ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
2047-
{ "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024,
2048-
SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
2049-
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
2050-
{ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K |
2051-
USE_FSR | SPI_NOR_QUAD_READ) },
2052-
{ "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
2053-
{ "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
2054-
{ "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096,
2055-
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
2056-
NO_CHIP_ERASE) },
2057-
{ "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
2058-
2059-
/* Micron */
2060-
{
2061-
"mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
2062-
SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
2063-
SPI_NOR_4B_OPCODES)
2064-
},
2065-
{ "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048,
2066-
SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
2067-
SPI_NOR_4B_OPCODES) },
2068-
20691998
/* Spansion/Cypress -- single (large) sector size only, at least
20701999
* for the chips listed here (without boot sectors).
20712000
*/
@@ -2123,42 +2052,6 @@ static const struct flash_info spi_nor_ids[] = {
21232052
SPI_NOR_DUAL_READ) },
21242053
{ "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
21252054

2126-
/* ST Microelectronics -- newer production may have feature updates */
2127-
{ "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
2128-
{ "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
2129-
{ "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
2130-
{ "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
2131-
{ "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
2132-
{ "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
2133-
{ "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
2134-
{ "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
2135-
{ "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
2136-
2137-
{ "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
2138-
{ "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
2139-
{ "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
2140-
{ "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
2141-
{ "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
2142-
{ "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
2143-
{ "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
2144-
{ "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
2145-
{ "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
2146-
2147-
{ "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
2148-
{ "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
2149-
{ "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
2150-
2151-
{ "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
2152-
{ "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
2153-
{ "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
2154-
2155-
{ "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
2156-
{ "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
2157-
{ "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
2158-
{ "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
2159-
{ "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
2160-
{ "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
2161-
21622055
/* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
21632056
{ "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
21642057
{ "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
@@ -2256,6 +2149,8 @@ static const struct spi_nor_manufacturer *manufacturers[] = {
22562149
&spi_nor_intel,
22572150
&spi_nor_issi,
22582151
&spi_nor_macronix,
2152+
&spi_nor_micron,
2153+
&spi_nor_st,
22592154
};
22602155

22612156
static const struct flash_info *
@@ -3040,14 +2935,6 @@ static void sst_set_default_init(struct spi_nor *nor)
30402935
nor->flags |= SNOR_F_HAS_LOCK;
30412936
}
30422937

3043-
static void st_micron_set_default_init(struct spi_nor *nor)
3044-
{
3045-
nor->flags |= SNOR_F_HAS_LOCK;
3046-
nor->flags &= ~SNOR_F_HAS_16BIT_SR;
3047-
nor->params.quad_enable = NULL;
3048-
nor->params.set_4byte_addr_mode = st_micron_set_4byte_addr_mode;
3049-
}
3050-
30512938
static void winbond_set_default_init(struct spi_nor *nor)
30522939
{
30532940
nor->params.set_4byte_addr_mode = winbond_set_4byte_addr_mode;
@@ -3062,11 +2949,6 @@ static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
30622949
{
30632950
/* Init flash parameters based on MFR */
30642951
switch (JEDEC_MFR(nor->info)) {
3065-
case SNOR_MFR_ST:
3066-
case SNOR_MFR_MICRON:
3067-
st_micron_set_default_init(nor);
3068-
break;
3069-
30702952
case SNOR_MFR_SST:
30712953
sst_set_default_init(nor);
30722954
break;

‎drivers/mtd/spi-nor/core.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -176,6 +176,8 @@ extern const struct spi_nor_manufacturer spi_nor_gigadevice;
176176
extern const struct spi_nor_manufacturer spi_nor_intel;
177177
extern const struct spi_nor_manufacturer spi_nor_issi;
178178
extern const struct spi_nor_manufacturer spi_nor_macronix;
179+
extern const struct spi_nor_manufacturer spi_nor_micron;
180+
extern const struct spi_nor_manufacturer spi_nor_st;
179181

180182
int spi_nor_write_enable(struct spi_nor *nor);
181183
int spi_nor_write_disable(struct spi_nor *nor);

‎drivers/mtd/spi-nor/micron-st.c

Lines changed: 153 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,153 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* Copyright (C) 2005, Intec Automation Inc.
4+
* Copyright (C) 2014, Freescale Semiconductor, Inc.
5+
*/
6+
7+
#include <linux/mtd/spi-nor.h>
8+
9+
#include "core.h"
10+
11+
static const struct flash_info micron_parts[] = {
12+
{ "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
13+
SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
14+
SPI_NOR_4B_OPCODES) },
15+
{ "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048,
16+
SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
17+
SPI_NOR_4B_OPCODES) },
18+
};
19+
20+
static const struct flash_info st_parts[] = {
21+
{ "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32,
22+
SECT_4K | SPI_NOR_QUAD_READ) },
23+
{ "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64,
24+
SPI_NOR_QUAD_READ) },
25+
{ "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64,
26+
SPI_NOR_QUAD_READ) },
27+
{ "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128,
28+
SECT_4K | SPI_NOR_QUAD_READ) },
29+
{ "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128,
30+
SECT_4K | SPI_NOR_QUAD_READ) },
31+
{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256,
32+
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
33+
{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256,
34+
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
35+
{ "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512,
36+
SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
37+
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
38+
{ "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K |
39+
USE_FSR | SPI_NOR_DUAL_READ |
40+
SPI_NOR_QUAD_READ) },
41+
{ "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512,
42+
SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
43+
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
44+
{ "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512,
45+
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
46+
{ "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024,
47+
SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
48+
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
49+
{ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024,
50+
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
51+
{ "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024,
52+
SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
53+
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
54+
{ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024,
55+
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
56+
{ "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048,
57+
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
58+
NO_CHIP_ERASE) },
59+
{ "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048,
60+
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
61+
NO_CHIP_ERASE) },
62+
{ "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096,
63+
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
64+
NO_CHIP_ERASE) },
65+
{ "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096,
66+
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
67+
NO_CHIP_ERASE) },
68+
69+
{ "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
70+
{ "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
71+
{ "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
72+
{ "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
73+
{ "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
74+
{ "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
75+
{ "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
76+
{ "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
77+
{ "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
78+
79+
{ "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
80+
{ "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
81+
{ "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
82+
{ "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
83+
{ "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
84+
{ "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
85+
{ "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
86+
{ "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
87+
{ "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
88+
89+
{ "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
90+
{ "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
91+
{ "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
92+
93+
{ "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
94+
{ "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
95+
{ "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
96+
97+
{ "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
98+
{ "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
99+
{ "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
100+
{ "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
101+
{ "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
102+
{ "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
103+
};
104+
105+
/**
106+
* st_micron_set_4byte_addr_mode() - Set 4-byte address mode for ST and Micron
107+
* flashes.
108+
* @nor: pointer to 'struct spi_nor'.
109+
* @enable: true to enter the 4-byte address mode, false to exit the 4-byte
110+
* address mode.
111+
*
112+
* Return: 0 on success, -errno otherwise.
113+
*/
114+
static int st_micron_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
115+
{
116+
int ret;
117+
118+
ret = spi_nor_write_enable(nor);
119+
if (ret)
120+
return ret;
121+
122+
ret = spi_nor_set_4byte_addr_mode(nor, enable);
123+
if (ret)
124+
return ret;
125+
126+
return spi_nor_write_disable(nor);
127+
}
128+
129+
static void micron_st_default_init(struct spi_nor *nor)
130+
{
131+
nor->flags |= SNOR_F_HAS_LOCK;
132+
nor->flags &= ~SNOR_F_HAS_16BIT_SR;
133+
nor->params.quad_enable = NULL;
134+
nor->params.set_4byte_addr_mode = st_micron_set_4byte_addr_mode;
135+
}
136+
137+
static const struct spi_nor_fixups micron_st_fixups = {
138+
.default_init = micron_st_default_init,
139+
};
140+
141+
const struct spi_nor_manufacturer spi_nor_micron = {
142+
.name = "micron",
143+
.parts = micron_parts,
144+
.nparts = ARRAY_SIZE(micron_parts),
145+
.fixups = &micron_st_fixups,
146+
};
147+
148+
const struct spi_nor_manufacturer spi_nor_st = {
149+
.name = "st",
150+
.parts = st_parts,
151+
.nparts = ARRAY_SIZE(st_parts),
152+
.fixups = &micron_st_fixups,
153+
};

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