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Roman YeryominKalle Valo
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rt2x00: add support for MT7620
Basic support for MT7620 built-in wireless radio was added to OpenWrt in r41441. It has seen some heavy cleaning and refactoring since in order to match the Kernel's code quality standards. Signed-off-by: Roman Yeryomin <roman@advem.lv> Signed-off-by: Daniel Golle <daniel@makrotopia.org> Acked-by: Stanislaw Gruszka <sgruszka@redhat.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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drivers/net/wireless/ralink/rt2x00/Kconfig

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -201,7 +201,7 @@ endif
201201

202202
config RT2800SOC
203203
tristate "Ralink WiSoC support"
204-
depends on SOC_RT288X || SOC_RT305X
204+
depends on SOC_RT288X || SOC_RT305X || SOC_MT7620
205205
select RT2X00_LIB_SOC
206206
select RT2X00_LIB_MMIO
207207
select RT2X00_LIB_CRYPTO

drivers/net/wireless/ralink/rt2x00/rt2800.h

Lines changed: 177 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -79,6 +79,7 @@
7979
#define RF5372 0x5372
8080
#define RF5390 0x5390
8181
#define RF5392 0x5392
82+
#define RF7620 0x7620
8283

8384
/*
8485
* Chipset revisions.
@@ -638,6 +639,24 @@
638639
#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
639640
#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
640641

642+
/*
643+
* MT7620 RF registers (reversed order)
644+
*/
645+
#define RF_CSR_CFG_DATA_MT7620 FIELD32(0x0000ff00)
646+
#define RF_CSR_CFG_REGNUM_MT7620 FIELD32(0x03ff0000)
647+
#define RF_CSR_CFG_WRITE_MT7620 FIELD32(0x00000010)
648+
#define RF_CSR_CFG_BUSY_MT7620 FIELD32(0x00000001)
649+
650+
/* undocumented registers for calibration of new MAC */
651+
#define RF_CONTROL0 0x0518
652+
#define RF_BYPASS0 0x051c
653+
#define RF_CONTROL1 0x0520
654+
#define RF_BYPASS1 0x0524
655+
#define RF_CONTROL2 0x0528
656+
#define RF_BYPASS2 0x052c
657+
#define RF_CONTROL3 0x0530
658+
#define RF_BYPASS3 0x0534
659+
641660
/*
642661
* EFUSE_CSR: RT30x0 EEPROM
643662
*/
@@ -1021,6 +1040,16 @@
10211040
#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
10221041
#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
10231042

1043+
/*
1044+
* MIMO_PS_CFG: MIMO Power-save Configuration
1045+
*/
1046+
#define MIMO_PS_CFG 0x1210
1047+
#define MIMO_PS_CFG_MMPS_BB_EN FIELD32(0x00000001)
1048+
#define MIMO_PS_CFG_MMPS_RX_ANT_NUM FIELD32(0x00000006)
1049+
#define MIMO_PS_CFG_MMPS_RF_EN FIELD32(0x00000008)
1050+
#define MIMO_PS_CFG_RX_STBY_POL FIELD32(0x00000010)
1051+
#define MIMO_PS_CFG_RX_RX_STBY0 FIELD32(0x00000020)
1052+
10241053
/*
10251054
* EDCA_AC0_CFG:
10261055
*/
@@ -1095,6 +1124,12 @@
10951124
#define TX_PWR_CFG_0_OFDM6_CH1 FIELD32(0x00f00000)
10961125
#define TX_PWR_CFG_0_OFDM12_CH0 FIELD32(0x0f000000)
10971126
#define TX_PWR_CFG_0_OFDM12_CH1 FIELD32(0xf0000000)
1127+
/* bits for new 2T devices */
1128+
#define TX_PWR_CFG_0B_1MBS_2MBS FIELD32(0x000000ff)
1129+
#define TX_PWR_CFG_0B_5MBS_11MBS FIELD32(0x0000ff00)
1130+
#define TX_PWR_CFG_0B_6MBS_9MBS FIELD32(0x00ff0000)
1131+
#define TX_PWR_CFG_0B_12MBS_18MBS FIELD32(0xff000000)
1132+
10981133

10991134
/*
11001135
* TX_PWR_CFG_1:
@@ -1117,6 +1152,11 @@
11171152
#define TX_PWR_CFG_1_MCS0_CH1 FIELD32(0x00f00000)
11181153
#define TX_PWR_CFG_1_MCS2_CH0 FIELD32(0x0f000000)
11191154
#define TX_PWR_CFG_1_MCS2_CH1 FIELD32(0xf0000000)
1155+
/* bits for new 2T devices */
1156+
#define TX_PWR_CFG_1B_24MBS_36MBS FIELD32(0x000000ff)
1157+
#define TX_PWR_CFG_1B_48MBS FIELD32(0x0000ff00)
1158+
#define TX_PWR_CFG_1B_MCS0_MCS1 FIELD32(0x00ff0000)
1159+
#define TX_PWR_CFG_1B_MCS2_MCS3 FIELD32(0xff000000)
11201160

11211161
/*
11221162
* TX_PWR_CFG_2:
@@ -1139,6 +1179,11 @@
11391179
#define TX_PWR_CFG_2_MCS8_CH1 FIELD32(0x00f00000)
11401180
#define TX_PWR_CFG_2_MCS10_CH0 FIELD32(0x0f000000)
11411181
#define TX_PWR_CFG_2_MCS10_CH1 FIELD32(0xf0000000)
1182+
/* bits for new 2T devices */
1183+
#define TX_PWR_CFG_2B_MCS4_MCS5 FIELD32(0x000000ff)
1184+
#define TX_PWR_CFG_2B_MCS6_MCS7 FIELD32(0x0000ff00)
1185+
#define TX_PWR_CFG_2B_MCS8_MCS9 FIELD32(0x00ff0000)
1186+
#define TX_PWR_CFG_2B_MCS10_MCS11 FIELD32(0xff000000)
11421187

11431188
/*
11441189
* TX_PWR_CFG_3:
@@ -1161,6 +1206,11 @@
11611206
#define TX_PWR_CFG_3_STBC0_CH1 FIELD32(0x00f00000)
11621207
#define TX_PWR_CFG_3_STBC2_CH0 FIELD32(0x0f000000)
11631208
#define TX_PWR_CFG_3_STBC2_CH1 FIELD32(0xf0000000)
1209+
/* bits for new 2T devices */
1210+
#define TX_PWR_CFG_3B_MCS12_MCS13 FIELD32(0x000000ff)
1211+
#define TX_PWR_CFG_3B_MCS14 FIELD32(0x0000ff00)
1212+
#define TX_PWR_CFG_3B_STBC_MCS0_MCS1 FIELD32(0x00ff0000)
1213+
#define TX_PWR_CFG_3B_STBC_MCS2_MSC3 FIELD32(0xff000000)
11641214

11651215
/*
11661216
* TX_PWR_CFG_4:
@@ -1175,6 +1225,9 @@
11751225
#define TX_PWR_CFG_4_STBC4_CH1 FIELD32(0x000000f0)
11761226
#define TX_PWR_CFG_4_STBC6_CH0 FIELD32(0x00000f00)
11771227
#define TX_PWR_CFG_4_STBC6_CH1 FIELD32(0x0000f000)
1228+
/* bits for new 2T devices */
1229+
#define TX_PWR_CFG_4B_STBC_MCS4_MCS5 FIELD32(0x000000ff)
1230+
#define TX_PWR_CFG_4B_STBC_MCS6 FIELD32(0x0000ff00)
11781231

11791232
/*
11801233
* TX_PIN_CFG:
@@ -1201,6 +1254,8 @@
12011254
#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
12021255
#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
12031256
#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
1257+
#define TX_PIN_CFG_RFRX_EN FIELD32(0x00100000)
1258+
#define TX_PIN_CFG_RFRX_POL FIELD32(0x00200000)
12041259
#define TX_PIN_CFG_PA_PE_A2_EN FIELD32(0x01000000)
12051260
#define TX_PIN_CFG_PA_PE_G2_EN FIELD32(0x02000000)
12061261
#define TX_PIN_CFG_PA_PE_A2_POL FIELD32(0x04000000)
@@ -1547,6 +1602,95 @@
15471602
#define TX_PWR_CFG_4_EXT_STBC4_CH2 FIELD32(0x0000000f)
15481603
#define TX_PWR_CFG_4_EXT_STBC6_CH2 FIELD32(0x00000f00)
15491604

1605+
/* TXn_RF_GAIN_CORRECT: RF Gain Correction for each RF_ALC[3:2]
1606+
* Unit: 0.1 dB, Range: -3.2 dB to 3.1 dB
1607+
*/
1608+
#define TX0_RF_GAIN_CORRECT 0x13a0
1609+
#define TX0_RF_GAIN_CORRECT_GAIN_CORR_0 FIELD32(0x0000003f)
1610+
#define TX0_RF_GAIN_CORRECT_GAIN_CORR_1 FIELD32(0x00003f00)
1611+
#define TX0_RF_GAIN_CORRECT_GAIN_CORR_2 FIELD32(0x003f0000)
1612+
#define TX0_RF_GAIN_CORRECT_GAIN_CORR_3 FIELD32(0x3f000000)
1613+
1614+
#define TX1_RF_GAIN_CORRECT 0x13a4
1615+
#define TX1_RF_GAIN_CORRECT_GAIN_CORR_0 FIELD32(0x0000003f)
1616+
#define TX1_RF_GAIN_CORRECT_GAIN_CORR_1 FIELD32(0x00003f00)
1617+
#define TX1_RF_GAIN_CORRECT_GAIN_CORR_2 FIELD32(0x003f0000)
1618+
#define TX1_RF_GAIN_CORRECT_GAIN_CORR_3 FIELD32(0x3f000000)
1619+
1620+
/* TXn_RF_GAIN_ATTEN: TXn RF Gain Attenuation Level
1621+
* Format: 7-bit, signed value
1622+
* Unit: 0.5 dB, Range: -20 dB to -5 dB
1623+
*/
1624+
#define TX0_RF_GAIN_ATTEN 0x13a8
1625+
#define TX0_RF_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000007f)
1626+
#define TX0_RF_GAIN_ATTEN_LEVEL_1 FIELD32(0x00007f00)
1627+
#define TX0_RF_GAIN_ATTEN_LEVEL_2 FIELD32(0x007f0000)
1628+
#define TX0_RF_GAIN_ATTEN_LEVEL_3 FIELD32(0x7f000000)
1629+
#define TX1_RF_GAIN_ATTEN 0x13ac
1630+
#define TX1_RF_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000007f)
1631+
#define TX1_RF_GAIN_ATTEN_LEVEL_1 FIELD32(0x00007f00)
1632+
#define TX1_RF_GAIN_ATTEN_LEVEL_2 FIELD32(0x007f0000)
1633+
#define TX1_RF_GAIN_ATTEN_LEVEL_3 FIELD32(0x7f000000)
1634+
1635+
/* TX_ALC_CFG_0: TX Automatic Level Control Configuration 0
1636+
* TX_ALC_LIMIT_n: TXn upper limit
1637+
* TX_ALC_CH_INIT_n: TXn channel initial transmission gain
1638+
* Unit: 0.5 dB, Range: 0 to 23.5 dB
1639+
*/
1640+
#define TX_ALC_CFG_0 0x13b0
1641+
#define TX_ALC_CFG_0_CH_INIT_0 FIELD32(0x0000003f)
1642+
#define TX_ALC_CFG_0_CH_INIT_1 FIELD32(0x00003f00)
1643+
#define TX_ALC_CFG_0_LIMIT_0 FIELD32(0x003f0000)
1644+
#define TX_ALC_CFG_0_LIMIT_1 FIELD32(0x3f000000)
1645+
1646+
/* TX_ALC_CFG_1: TX Automatic Level Control Configuration 1
1647+
* TX_TEMP_COMP: TX Power Temperature Compensation
1648+
* Unit: 0.5 dB, Range: -10 dB to 10 dB
1649+
* TXn_GAIN_FINE: TXn Gain Fine Adjustment
1650+
* Unit: 0.1 dB, Range: -0.8 dB to 0.7 dB
1651+
* RF_TOS_DLY: Sets the RF_TOS_EN assertion delay after
1652+
* deassertion of PA_PE.
1653+
* Unit: 0.25 usec
1654+
* TXn_RF_GAIN_ATTEN: TXn RF gain attentuation selector
1655+
* RF_TOS_TIMEOUT: time-out value for RF_TOS_ENABLE
1656+
* deassertion if RF_TOS_DONE is missing.
1657+
* Unit: 0.25 usec
1658+
* RF_TOS_ENABLE: TX offset calibration enable
1659+
* ROS_BUSY_EN: RX offset calibration busy enable
1660+
*/
1661+
#define TX_ALC_CFG_1 0x13b4
1662+
#define TX_ALC_CFG_1_TX_TEMP_COMP FIELD32(0x0000003f)
1663+
#define TX_ALC_CFG_1_TX0_GAIN_FINE FIELD32(0x00000f00)
1664+
#define TX_ALC_CFG_1_TX1_GAIN_FINE FIELD32(0x0000f000)
1665+
#define TX_ALC_CFG_1_RF_TOS_DLY FIELD32(0x00070000)
1666+
#define TX_ALC_CFG_1_TX0_RF_GAIN_ATTEN FIELD32(0x00300000)
1667+
#define TX_ALC_CFG_1_TX1_RF_GAIN_ATTEN FIELD32(0x00c00000)
1668+
#define TX_ALC_CFG_1_RF_TOS_TIMEOUT FIELD32(0x3f000000)
1669+
#define TX_ALC_CFG_1_RF_TOS_ENABLE FIELD32(0x40000000)
1670+
#define TX_ALC_CFG_1_ROS_BUSY_EN FIELD32(0x80000000)
1671+
1672+
/* TXn_BB_GAIN_ATTEN: TXn RF Gain Attenuation Level
1673+
* Format: 5-bit signed values
1674+
* Unit: 0.5 dB, Range: -8 dB to 7 dB
1675+
*/
1676+
#define TX0_BB_GAIN_ATTEN 0x13c0
1677+
#define TX0_BB_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000001f)
1678+
#define TX0_BB_GAIN_ATTEN_LEVEL_1 FIELD32(0x00001f00)
1679+
#define TX0_BB_GAIN_ATTEN_LEVEL_2 FIELD32(0x001f0000)
1680+
#define TX0_BB_GAIN_ATTEN_LEVEL_3 FIELD32(0x1f000000)
1681+
#define TX1_BB_GAIN_ATTEN 0x13c4
1682+
#define TX1_BB_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000001f)
1683+
#define TX1_BB_GAIN_ATTEN_LEVEL_1 FIELD32(0x00001f00)
1684+
#define TX1_BB_GAIN_ATTEN_LEVEL_2 FIELD32(0x001f0000)
1685+
#define TX1_BB_GAIN_ATTEN_LEVEL_3 FIELD32(0x1f000000)
1686+
1687+
/* TX_ALC_VGA3: TX Automatic Level Correction Variable Gain Amplifier 3 */
1688+
#define TX_ALC_VGA3 0x13c8
1689+
#define TX_ALC_VGA3_TX0_ALC_VGA3 FIELD32(0x0000001f)
1690+
#define TX_ALC_VGA3_TX1_ALC_VGA3 FIELD32(0x00001f00)
1691+
#define TX_ALC_VGA3_TX0_ALC_VGA2 FIELD32(0x001f0000)
1692+
#define TX_ALC_VGA3_TX1_ALC_VGA2 FIELD32(0x1f000000)
1693+
15501694
/* TX_PWR_CFG_7 */
15511695
#define TX_PWR_CFG_7 0x13d4
15521696
#define TX_PWR_CFG_7_OFDM54_CH0 FIELD32(0x0000000f)
@@ -1555,6 +1699,10 @@
15551699
#define TX_PWR_CFG_7_MCS7_CH0 FIELD32(0x000f0000)
15561700
#define TX_PWR_CFG_7_MCS7_CH1 FIELD32(0x00f00000)
15571701
#define TX_PWR_CFG_7_MCS7_CH2 FIELD32(0x0f000000)
1702+
/* bits for new 2T devices */
1703+
#define TX_PWR_CFG_7B_54MBS FIELD32(0x000000ff)
1704+
#define TX_PWR_CFG_7B_MCS7 FIELD32(0x00ff0000)
1705+
15581706

15591707
/* TX_PWR_CFG_8 */
15601708
#define TX_PWR_CFG_8 0x13d8
@@ -1564,12 +1712,17 @@
15641712
#define TX_PWR_CFG_8_MCS23_CH0 FIELD32(0x000f0000)
15651713
#define TX_PWR_CFG_8_MCS23_CH1 FIELD32(0x00f00000)
15661714
#define TX_PWR_CFG_8_MCS23_CH2 FIELD32(0x0f000000)
1715+
/* bits for new 2T devices */
1716+
#define TX_PWR_CFG_8B_MCS15 FIELD32(0x000000ff)
1717+
15671718

15681719
/* TX_PWR_CFG_9 */
15691720
#define TX_PWR_CFG_9 0x13dc
15701721
#define TX_PWR_CFG_9_STBC7_CH0 FIELD32(0x0000000f)
15711722
#define TX_PWR_CFG_9_STBC7_CH1 FIELD32(0x000000f0)
15721723
#define TX_PWR_CFG_9_STBC7_CH2 FIELD32(0x00000f00)
1724+
/* bits for new 2T devices */
1725+
#define TX_PWR_CFG_9B_STBC_MCS7 FIELD32(0x000000ff)
15731726

15741727
/*
15751728
* RX_FILTER_CFG: RX configuration register.
@@ -2137,11 +2290,14 @@ struct mac_iveiv_entry {
21372290
#define RFCSR1_TX1_PD FIELD8(0x20)
21382291
#define RFCSR1_RX2_PD FIELD8(0x40)
21392292
#define RFCSR1_TX2_PD FIELD8(0x80)
2293+
#define RFCSR1_TX2_EN_MT7620 FIELD8(0x02)
21402294

21412295
/*
21422296
* RFCSR 2:
21432297
*/
21442298
#define RFCSR2_RESCAL_EN FIELD8(0x80)
2299+
#define RFCSR2_RX2_EN_MT7620 FIELD8(0x02)
2300+
#define RFCSR2_TX2_EN_MT7620 FIELD8(0x20)
21452301

21462302
/*
21472303
* RFCSR 3:
@@ -2159,6 +2315,12 @@ struct mac_iveiv_entry {
21592315
#define RFCSR3_BIT4 FIELD8(0x10)
21602316
#define RFCSR3_BIT5 FIELD8(0x20)
21612317

2318+
/*
2319+
* RFCSR 4:
2320+
* VCOCAL_EN used by MT7620
2321+
*/
2322+
#define RFCSR4_VCOCAL_EN FIELD8(0x80)
2323+
21622324
/*
21632325
* FRCSR 5:
21642326
*/
@@ -2214,6 +2376,7 @@ struct mac_iveiv_entry {
22142376
*/
22152377
#define RFCSR13_TX_POWER FIELD8(0x1f)
22162378
#define RFCSR13_DR0 FIELD8(0xe0)
2379+
#define RFCSR13_RDIV_MT7620 FIELD8(0x03)
22172380

22182381
/*
22192382
* RFCSR 15:
@@ -2224,6 +2387,8 @@ struct mac_iveiv_entry {
22242387
* RFCSR 16:
22252388
*/
22262389
#define RFCSR16_TXMIXER_GAIN FIELD8(0x07)
2390+
#define RFCSR16_RF_PLL_FREQ_SEL_MT7620 FIELD8(0x0F)
2391+
#define RFCSR16_SDM_MODE_MT7620 FIELD8(0xE0)
22272392

22282393
/*
22292394
* RFCSR 17:
@@ -2236,6 +2401,8 @@ struct mac_iveiv_entry {
22362401
/* RFCSR 18 */
22372402
#define RFCSR18_XO_TUNE_BYPASS FIELD8(0x40)
22382403

2404+
/* RFCSR 19 */
2405+
#define RFCSR19_K FIELD8(0x03)
22392406

22402407
/*
22412408
* RFCSR 20:
@@ -2246,11 +2413,14 @@ struct mac_iveiv_entry {
22462413
* RFCSR 21:
22472414
*/
22482415
#define RFCSR21_RX_LO2_EN FIELD8(0x08)
2416+
#define RFCSR21_BIT1 FIELD8(0x01)
2417+
#define RFCSR21_BIT8 FIELD8(0x80)
22492418

22502419
/*
22512420
* RFCSR 22:
22522421
*/
22532422
#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
2423+
#define RFCSR22_FREQPLAN_D_MT7620 FIELD8(0x07)
22542424

22552425
/*
22562426
* RFCSR 23:
@@ -2272,6 +2442,11 @@ struct mac_iveiv_entry {
22722442
#define RFCSR27_R3 FIELD8(0x30)
22732443
#define RFCSR27_R4 FIELD8(0x40)
22742444

2445+
/*
2446+
* RFCSR 28:
2447+
*/
2448+
#define RFCSR28_CH11_HT40 FIELD8(0x04)
2449+
22752450
/*
22762451
* RFCSR 29:
22772452
*/
@@ -2333,6 +2508,7 @@ struct mac_iveiv_entry {
23332508
*/
23342509
#define RFCSR42_BIT1 FIELD8(0x01)
23352510
#define RFCSR42_BIT4 FIELD8(0x08)
2511+
#define RFCSR42_TX2_EN_MT7620 FIELD8(0x40)
23362512

23372513
/*
23382514
* RFCSR 49:
@@ -2435,6 +2611,7 @@ enum rt2800_eeprom_word {
24352611
EEPROM_TSSI_BOUND_BG5,
24362612
EEPROM_TXPOWER_A1,
24372613
EEPROM_TXPOWER_A2,
2614+
EEPROM_TXPOWER_INIT,
24382615
EEPROM_TSSI_BOUND_A1,
24392616
EEPROM_TSSI_BOUND_A2,
24402617
EEPROM_TSSI_BOUND_A3,

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