From 5b2c9121ef7cf9745f0c1df10544fd0ba6a6a38c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rapha=C3=ABl=20Teysseyre?= Date: Wed, 24 Jun 2015 09:19:45 +0200 Subject: [PATCH] gpio/xilinx: Use correct address when setting initial values. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit xgpio_save_regs() is used in this driver to setup the initial values of the registers in the hardware. The relevant registers at that time are: 0x0 -> channel 0 data (32 bits, one for each GPIO on this channel). 0x4 -> channel 0 tri, controls in/out status for each GPIO of this channel. 0x8 -> channel 1 data 0xC -> channel 1 tri gpio-xilinx.c defines these: XGPIO_DATA_OFFSET (0x0) XGPIO_TRI_OFFSET (0x4) XGPIO_CHANNEL_OFFSET 0x8 Before this patch, the "data" register value of channel 1 was written at 0x4 intead of 0x8 (overwriting the channel 0 "tri" register), and the "tri" register value for channel 1 was written at 0x8 instead of 0xC. Signed-off-by: Raphaël Teysseyre Reviewed-by: Michal Simek Reviewed-by: Alexandre Courbot Signed-off-by: Linus Walleij --- drivers/gpio/gpio-xilinx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c index 77fe5d3cb105b9..d5284dfe01fe16 100644 --- a/drivers/gpio/gpio-xilinx.c +++ b/drivers/gpio/gpio-xilinx.c @@ -220,9 +220,9 @@ static void xgpio_save_regs(struct of_mm_gpio_chip *mm_gc) if (!chip->gpio_width[1]) return; - xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET + XGPIO_TRI_OFFSET, + xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET + XGPIO_CHANNEL_OFFSET, chip->gpio_state[1]); - xgpio_writereg(mm_gc->regs + XGPIO_TRI_OFFSET + XGPIO_TRI_OFFSET, + xgpio_writereg(mm_gc->regs + XGPIO_TRI_OFFSET + XGPIO_CHANNEL_OFFSET, chip->gpio_dir[1]); }