Please sign in to comment.
clk: vt8500: Fix device clock divisor calculations
When calculating device clock divisor values in set_rate and round_rate, we do a simple integer divide. If parent_rate / rate has a fraction, this is dropped which results in the device clock being set too high. This patch corrects the problem by adding 1 to the calculated divisor if the division would have had a decimal result. Signed-off-by: Tony Prisk <email@example.com> Signed-off-by: Mike Turquette <firstname.lastname@example.org>
- Loading branch information...