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Merge tag 'dt-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/…
…soc/soc
Pull ARM SoC DT updates from Arnd Bergmann:
"As usual, the bulk of work in the SoC tree goes into DT files, this
time with a roughly even split between 32-bit and 64-bit SoCs rather
than the usual mostly 64-bit changes.
New SoCs:
- Microchip SAMA7 SoC family based on Cortex-A7, a new 32-bit
platform based on the older SAMA5 series.
- Qualcomm Snapdragon SDM636 and SM8150, variations of the existing
phone SoCs.
- Renesas R-Car H3e-2G and M3e-2G SoCs, variations of older Renesas
SoCs.
New boards:
- Marvell CN913x reference boards
- ASpeed AST2600 BMC implementations for Facebook Cloudripper, Elbert
and Fuji server boards.
- Snapdragon 665 based Sony Xperia 10II
- Snapdragon MSM8916 based Xiaomi Redmi 2
- Snapdragon MSM8226 based Samsung Galaxy S3 Neo
- NXP i.MX based 32-bit boards:
- DHCOM based PicoITX
- DHSOM based DRC0ỉ
- SolidRun SolidSense
- SKOV i.MX6 boards.
- NXP i.MX based 64-bit boards:
- Nitrogen8 SoM and MNT Reform2
- LS1088A based Traverse Ten64
- i.MX8M based GW7902.
- NVIDIA Jetson TX2 NX Developer Kit
- 4KOpen STiH418-b2264 development board
- ux500 based Samsung phones: Gavini, Codina and Kyle
- TI AM335x based Sancloud BBE Lite
- ixp4xx dts files to replace all old board files
Other changes:
- Treewide fixes for dtc warnings
- Rockchips i/o domain support
- TI OMAP/AM3 CPSW switch driver support
- Improved device support for allwinner, aspeed, qualcomm, NXP,
nvidia, Renesas, Samsung, Amlogic, Mediatek, ixp4xx, stm32, sti,
OMAP and actions"
* tag 'dt-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (412 commits)
arm/arm64: dts: Fix remaining dtc 'unit_address_format' warnings
ARM: dts: rockchip: Add SFC to RV1108
arm64: dts: marvell: armada-37xx: Extend PCIe MEM space
ARM: dts: aspeed: p10bmc: Add power control pins
ARM: dts: aspeed: cloudripper: Add comments for "mdio1"
ARM: dts: aspeed: minipack: Update flash partition table
dt-bindings: arm: fsl: Add Traverse Ten64 (LS1088A) board
dt-bindings: vendor-prefixes: add Traverse Technologies
arm64: dts: add device tree for Traverse Ten64 (LS1088A)
arm64: dts: ls1088a: add missing PMU node
arm64: dts: ls1088a: add internal PCS for DPMAC1 node
ARM: dts: imx6qp-prtwd3: configure ENET_REF clock to 125MHz
ARM: dts: vf610-zii-dev-rev-b: Remove #address-cells and #size-cells property from at93c46d dt node
ARM: dts: add SKOV imx6q and imx6dl based boards
dt-bindings: arm: fsl: add SKOV imx6q and imx6dl based boards
dt-bindings: vendor-prefixes: Add an entry for SKOV A/S
arm64: dts: imx8mq-reform2: add sound support
arm64: dts: imx8m: drop interrupt-affinity for pmu
arm64: dts: imx8qxp: update pmu compatible
arm64: dts: imx8mm: update pmu compatible
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,77 @@ | ||
| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| %YAML 1.2 | ||
| --- | ||
| $id: http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml# | ||
| $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
|
|
||
| title: Aspeed SGPIO controller | ||
|
|
||
| maintainers: | ||
| - Andrew Jeffery <andrew@aj.id.au> | ||
|
|
||
| description: | ||
| This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC, | ||
| AST2600 have two sgpio master one with 128 pins another one with 80 pins, | ||
| AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial | ||
| GPIO pins can be programmed to support the following options | ||
| - Support interrupt option for each input port and various interrupt | ||
| sensitivity option (level-high, level-low, edge-high, edge-low) | ||
| - Support reset tolerance option for each output port | ||
| - Directly connected to APB bus and its shift clock is from APB bus clock | ||
| divided by a programmable value. | ||
| - Co-work with external signal-chained TTL components (74LV165/74LV595) | ||
|
|
||
| properties: | ||
| compatible: | ||
| enum: | ||
| - aspeed,ast2400-sgpio | ||
| - aspeed,ast2500-sgpio | ||
| - aspeed,ast2600-sgpiom | ||
|
|
||
| reg: | ||
| maxItems: 1 | ||
|
|
||
| gpio-controller: true | ||
|
|
||
| '#gpio-cells': | ||
| const: 2 | ||
|
|
||
| interrupts: | ||
| maxItems: 1 | ||
|
|
||
| interrupt-controller: true | ||
|
|
||
| clocks: | ||
| maxItems: 1 | ||
|
|
||
| ngpios: true | ||
|
|
||
| bus-frequency: true | ||
|
|
||
| required: | ||
| - compatible | ||
| - reg | ||
| - gpio-controller | ||
| - '#gpio-cells' | ||
| - interrupts | ||
| - interrupt-controller | ||
| - ngpios | ||
| - clocks | ||
| - bus-frequency | ||
|
|
||
| additionalProperties: false | ||
|
|
||
| examples: | ||
| - | | ||
| #include <dt-bindings/clock/aspeed-clock.h> | ||
| sgpio: sgpio@1e780200 { | ||
| #gpio-cells = <2>; | ||
| compatible = "aspeed,ast2500-sgpio"; | ||
| gpio-controller; | ||
| interrupts = <40>; | ||
| reg = <0x1e780200 0x0100>; | ||
| clocks = <&syscon ASPEED_CLK_APB>; | ||
| interrupt-controller; | ||
| ngpios = <80>; | ||
| bus-frequency = <12000000>; | ||
| }; |
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