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Merge tag 'cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git…

…/arm/arm-soc

Pull "ARM: cleanups of io includes" from Olof Johansson:
 "Rob Herring has done a sweeping change cleaning up all of the
  mach/io.h includes, moving some of the oft-repeated macros to a common
  location and removing a bunch of boiler plate.  This is another step
  closer to a common zImage for multiple platforms."

Fix up various fairly trivial conflicts (<mach/io.h> removal vs changes
around it, tegra localtimer.o is *still* gone, yadda-yadda).

* tag 'cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (29 commits)
  ARM: tegra: Include assembler.h in sleep.S to fix build break
  ARM: pxa: use common IOMEM definition
  ARM: dma-mapping: convert ARCH_HAS_DMA_SET_COHERENT_MASK to kconfig symbol
  ARM: __io abuse cleanup
  ARM: create a common IOMEM definition
  ARM: iop13xx: fix missing declaration of iop13xx_init_early
  ARM: fix ioremap/iounmap for !CONFIG_MMU
  ARM: kill off __mem_pci
  ARM: remove bunch of now unused mach/io.h files
  ARM: make mach/io.h include optional
  ARM: clps711x: remove unneeded include of mach/io.h
  ARM: dove: add explicit include of dove.h to addr-map.c
  ARM: at91: add explicit include of hardware.h to uncompressor
  ARM: ep93xx: clean-up mach/io.h
  ARM: tegra: clean-up mach/io.h
  ARM: orion5x: clean-up mach/io.h
  ARM: davinci: remove unneeded mach/io.h include
  [media] davinci: remove includes of mach/io.h
  ARM: OMAP: Remove remaining includes for mach/io.h
  ARM: msm: clean-up mach/io.h
  ...
  • Loading branch information...
commit 820d41cf0cd0e94a5661e093821e2e5c6b36a9d8 2 parents 6268b32 + 88b4868
Linus Torvalds authored

Showing 162 changed files with 336 additions and 1,365 deletions. Show diff stats Hide diff stats

  1. +27 0 arch/arm/Kconfig
  2. +2 0  arch/arm/include/asm/assembler.h
  3. +33 38 arch/arm/include/asm/io.h
  4. +1 0  arch/arm/kernel/debug.S
  5. +1 0  arch/arm/kernel/entry-armv.S
  6. +0 31 arch/arm/mach-at91/include/mach/io.h
  7. +1 0  arch/arm/mach-at91/include/mach/uncompress.h
  8. +0 33 arch/arm/mach-bcmring/include/mach/io.h
  9. +0 36 arch/arm/mach-clps711x/include/mach/io.h
  10. +0 1  arch/arm/mach-clps711x/include/mach/uncompress.h
  11. +4 4 arch/arm/mach-cns3xxx/core.c
  12. +1 1  arch/arm/mach-cns3xxx/devices.c
  13. +0 17 arch/arm/mach-cns3xxx/include/mach/io.h
  14. +0 1  arch/arm/mach-davinci/include/mach/entry-macro.S
  15. +0 6 arch/arm/mach-davinci/include/mach/hardware.h
  16. +0 24 arch/arm/mach-davinci/include/mach/io.h
  17. +2 0  arch/arm/mach-davinci/include/mach/uncompress.h
  18. +1 0  arch/arm/mach-dove/addr-map.c
  19. +0 1  arch/arm/mach-dove/include/mach/io.h
  20. +15 0 arch/arm/mach-ebsa110/core.c
  21. +0 9 arch/arm/mach-ebsa110/include/mach/io.h
  22. +0 22 arch/arm/mach-ep93xx/include/mach/io.h
  23. +0 26 arch/arm/mach-exynos/include/mach/io.h
  24. +0 13 arch/arm/mach-footbridge/include/mach/io.h
  25. +0 18 arch/arm/mach-gemini/include/mach/io.h
  26. +0 22 arch/arm/mach-h720x/include/mach/io.h
  27. +0 7 arch/arm/mach-highbank/include/mach/io.h
  28. +5 5 arch/arm/mach-imx/mm-imx3.c
  29. +0 1  arch/arm/mach-integrator/include/mach/io.h
  30. +0 13 arch/arm/mach-iop13xx/include/mach/io.h
  31. +1 0  arch/arm/mach-iop13xx/include/mach/iop13xx.h
  32. +12 8 arch/arm/mach-iop13xx/io.c
  33. +1 0  arch/arm/mach-iop13xx/iq81340mc.c
  34. +1 0  arch/arm/mach-iop13xx/iq81340sc.c
  35. +6 0 arch/arm/mach-iop13xx/pci.h
  36. +0 1  arch/arm/mach-iop32x/include/mach/io.h
  37. +0 1  arch/arm/mach-iop33x/include/mach/io.h
  38. +0 1  arch/arm/mach-ixp2000/include/mach/io.h
  39. +0 1  arch/arm/mach-ixp23xx/include/mach/io.h
  40. +2 0  arch/arm/mach-ixp4xx/avila-setup.c
  41. +33 0 arch/arm/mach-ixp4xx/common.c
  42. +2 0  arch/arm/mach-ixp4xx/coyote-setup.c
  43. +1 0  arch/arm/mach-ixp4xx/dsmg600-setup.c
  44. +1 0  arch/arm/mach-ixp4xx/fsg-setup.c
  45. +1 0  arch/arm/mach-ixp4xx/gateway7001-setup.c
  46. +1 0  arch/arm/mach-ixp4xx/goramo_mlr.c
  47. +1 0  arch/arm/mach-ixp4xx/gtwx5715-setup.c
  48. +0 2  arch/arm/mach-ixp4xx/include/mach/hardware.h
  49. +1 23 arch/arm/mach-ixp4xx/include/mach/io.h
  50. +1 0  arch/arm/mach-ixp4xx/include/mach/platform.h
  51. +4 0 arch/arm/mach-ixp4xx/ixdp425-setup.c
  52. +1 0  arch/arm/mach-ixp4xx/nas100d-setup.c
  53. +1 0  arch/arm/mach-ixp4xx/nslu2-setup.c
  54. +3 0  arch/arm/mach-ixp4xx/omixp-setup.c
  55. +1 0  arch/arm/mach-ixp4xx/vulcan-setup.c
  56. +1 0  arch/arm/mach-ixp4xx/wg302v2-setup.c
  57. +0 2  arch/arm/mach-kirkwood/include/mach/io.h
  58. +0 19 arch/arm/mach-ks8695/include/mach/io.h
  59. +0 27 arch/arm/mach-lpc32xx/include/mach/io.h
  60. +0 6 arch/arm/mach-mmp/include/mach/addr-map.h
  61. +0 21 arch/arm/mach-mmp/include/mach/io.h
  62. +6 0 arch/arm/mach-msm/board-halibut.c
  63. +6 0 arch/arm/mach-msm/board-trout.c
  64. +0 36 arch/arm/mach-msm/include/mach/io.h
  65. +6 6 arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
  66. +4 0 arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
  67. +4 0 arch/arm/mach-msm/include/mach/msm_iomap-8960.h
  68. +4 0 arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
  69. +4 0 arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
  70. +0 6 arch/arm/mach-msm/include/mach/msm_iomap.h
  71. +3 5 arch/arm/mach-msm/io.c
  72. +0 2  arch/arm/mach-mv78xx0/include/mach/io.h
  73. +0 6 arch/arm/mach-mxs/include/mach/hardware.h
  74. +0 22 arch/arm/mach-mxs/include/mach/io.h
  75. +1 1  arch/arm/mach-netx/generic.c
  76. +1 1  arch/arm/mach-netx/include/mach/hardware.h
  77. +0 28 arch/arm/mach-netx/include/mach/io.h
  78. +8 8 arch/arm/mach-netx/include/mach/netx-regs.h
  79. +0 22 arch/arm/mach-nomadik/include/mach/io.h
  80. +1 0  arch/arm/mach-omap1/ams-delta-fiq-handler.S
  81. +0 1  arch/arm/mach-omap1/include/mach/entry-macro.S
  82. +0 46 arch/arm/mach-omap1/include/mach/io.h
  83. +0 6 arch/arm/mach-omap1/iomap.h
  84. +0 2  arch/arm/mach-omap1/sleep.S
  85. +0 1  arch/arm/mach-omap1/sram.S
  86. +1 0  arch/arm/mach-omap2/clock3xxx_data.c
  87. +1 0  arch/arm/mach-omap2/clock44xx_data.c
  88. +0 49 arch/arm/mach-omap2/include/mach/io.h
  89. +0 6 arch/arm/mach-omap2/iomap.h
  90. +9 0 arch/arm/mach-orion5x/common.h
  91. +0 33 arch/arm/mach-orion5x/include/mach/io.h
  92. +1 0  arch/arm/mach-orion5x/pci.c
  93. +1 0  arch/arm/mach-orion5x/tsx09-common.c
  94. +0 22 arch/arm/mach-picoxcell/include/mach/io.h
  95. +0 21 arch/arm/mach-pnx4008/include/mach/io.h
  96. +0 16 arch/arm/mach-prima2/include/mach/io.h
  97. +1 0  arch/arm/mach-pxa/Kconfig
  98. +1 0  arch/arm/mach-pxa/clock-pxa2xx.c
  99. +1 0  arch/arm/mach-pxa/corgi_pm.c
  100. +1 0  arch/arm/mach-pxa/cpufreq-pxa3xx.c
  101. +0 6 arch/arm/mach-pxa/include/mach/hardware.h
  102. +0 20 arch/arm/mach-pxa/include/mach/io.h
  103. +1 0  arch/arm/mach-pxa/mfp-pxa2xx.c
  104. +1 0  arch/arm/mach-pxa/pxa2xx.c
  105. +1 0  arch/arm/mach-pxa/pxa300.c
  106. +1 0  arch/arm/mach-pxa/pxa320.c
  107. +1 0  arch/arm/mach-pxa/sharpsl_pm.c
  108. +1 1  arch/arm/mach-realview/include/mach/hardware.h
  109. +0 28 arch/arm/mach-realview/include/mach/io.h
  110. +0 6 arch/arm/mach-rpc/include/mach/hardware.h
  111. +0 5 arch/arm/mach-rpc/include/mach/io.h
  112. +0 5 arch/arm/mach-s3c24xx/include/mach/io.h
  113. +0 18 arch/arm/mach-s3c64xx/include/mach/io.h
  114. +0 25 arch/arm/mach-s5p64x0/include/mach/io.h
  115. +0 18 arch/arm/mach-s5pc100/include/mach/io.h
  116. +0 26 arch/arm/mach-s5pv210/include/mach/io.h
  117. +0 20 arch/arm/mach-sa1100/include/mach/io.h
  118. +0 2  arch/arm/mach-shark/include/mach/io.h
  119. +1 1  arch/arm/mach-shmobile/board-ag5evm.c
  120. +1 1  arch/arm/mach-shmobile/board-bonito.c
  121. +1 1  arch/arm/mach-shmobile/board-kota2.c
  122. +0 9 arch/arm/mach-shmobile/include/mach/io.h
  123. +2 2 arch/arm/mach-shmobile/intc-r8a7779.c
  124. +2 2 arch/arm/mach-shmobile/intc-sh73a0.c
  125. +2 2 arch/arm/mach-shmobile/smp-r8a7779.c
  126. +10 10 arch/arm/mach-shmobile/smp-sh73a0.c
  127. +1 0  arch/arm/mach-spear3xx/clock.c
  128. +0 19 arch/arm/mach-spear3xx/include/mach/io.h
  129. +1 0  arch/arm/mach-spear6xx/clock.c
  130. +0 20 arch/arm/mach-spear6xx/include/mach/io.h
  131. +0 1  arch/arm/mach-tegra/include/mach/debug-macro.S
  132. +0 49 arch/arm/mach-tegra/include/mach/io.h
  133. +42 0 arch/arm/mach-tegra/include/mach/iomap.h
  134. +1 0  arch/arm/mach-tegra/io.c
  135. +3 1 arch/arm/mach-tegra/sleep.S
  136. +0 20 arch/arm/mach-u300/include/mach/io.h
  137. +0 6 arch/arm/mach-u300/include/mach/u300-regs.h
  138. +1 1  arch/arm/mach-ux500/include/mach/hardware.h
  139. +0 22 arch/arm/mach-ux500/include/mach/io.h
  140. +0 28 arch/arm/mach-versatile/include/mach/io.h
  141. +0 25 arch/arm/mach-vexpress/include/mach/io.h
  142. +0 26 arch/arm/mach-vt8500/include/mach/io.h
  143. +0 30 arch/arm/mach-w90x900/include/mach/io.h
  144. +0 33 arch/arm/mach-zynq/include/mach/io.h
  145. +14 3 arch/arm/mm/ioremap.c
  146. +6 2 arch/arm/mm/nommu.c
  147. +2 5 arch/arm/plat-mxc/include/mach/hardware.h
  148. +0 39 arch/arm/plat-mxc/include/mach/io.h
  149. +0 6 arch/arm/plat-omap/include/plat/hardware.h
  150. +0 1  arch/arm/plat-omap/include/plat/sdrc.h
  151. +0 1  arch/arm/plat-omap/include/plat/usb.h
  152. +0 6 arch/arm/plat-spear/include/plat/hardware.h
  153. +0 22 arch/arm/plat-spear/include/plat/io.h
  154. +0 1  drivers/media/video/davinci/vpbe_osd.c
  155. +0 1  drivers/media/video/davinci/vpbe_venc.c
  156. +1 0  drivers/rtc/rtc-sa1100.c
  157. +0 1  drivers/video/omap2/vrfb.c
  158. +1 0  drivers/watchdog/sa1100_wdt.c
  159. +1 1  include/linux/dma-mapping.h
  160. +1 0  sound/arm/pxa2xx-ac97-lib.c
  161. +1 0  sound/arm/pxa2xx-ac97.c
  162. +1 0  sound/soc/pxa/pxa2xx-ac97.c
27 arch/arm/Kconfig
@@ -179,6 +179,9 @@ config ZONE_DMA
179 179 config NEED_DMA_MAP_STATE
180 180 def_bool y
181 181
  182 +config ARCH_HAS_DMA_SET_COHERENT_MASK
  183 + bool
  184 +
182 185 config GENERIC_ISA_DMA
183 186 bool
184 187
@@ -216,6 +219,13 @@ config ARM_PATCH_PHYS_VIRT
216 219 this feature (eg, building a kernel for a single machine) and
217 220 you need to shrink the kernel to the minimal size.
218 221
  222 +config NEED_MACH_IO_H
  223 + bool
  224 + help
  225 + Select this when mach/io.h is required to provide special
  226 + definitions for this platform. The need for mach/io.h should
  227 + be avoided when possible.
  228 +
219 229 config NEED_MACH_MEMORY_H
220 230 bool
221 231 help
@@ -267,6 +277,7 @@ config ARCH_INTEGRATOR
267 277 select GENERIC_CLOCKEVENTS
268 278 select PLAT_VERSATILE
269 279 select PLAT_VERSATILE_FPGA_IRQ
  280 + select NEED_MACH_IO_H
270 281 select NEED_MACH_MEMORY_H
271 282 select SPARSE_IRQ
272 283 help
@@ -406,6 +417,7 @@ config ARCH_EBSA110
406 417 select ISA
407 418 select NO_IOPORT
408 419 select ARCH_USES_GETTIMEOFFSET
  420 + select NEED_MACH_IO_H
409 421 select NEED_MACH_MEMORY_H
410 422 help
411 423 This is an evaluation board for the StrongARM processor available
@@ -432,6 +444,7 @@ config ARCH_FOOTBRIDGE
432 444 select FOOTBRIDGE
433 445 select GENERIC_CLOCKEVENTS
434 446 select HAVE_IDE
  447 + select NEED_MACH_IO_H
435 448 select NEED_MACH_MEMORY_H
436 449 help
437 450 Support for systems based on the DC21285 companion chip
@@ -483,6 +496,7 @@ config ARCH_IOP13XX
483 496 select PCI
484 497 select ARCH_SUPPORTS_MSI
485 498 select VMSPLIT_1G
  499 + select NEED_MACH_IO_H
486 500 select NEED_MACH_MEMORY_H
487 501 select NEED_RET_TO_USER
488 502 help
@@ -492,6 +506,7 @@ config ARCH_IOP32X
492 506 bool "IOP32x-based"
493 507 depends on MMU
494 508 select CPU_XSCALE
  509 + select NEED_MACH_IO_H
495 510 select NEED_RET_TO_USER
496 511 select PLAT_IOP
497 512 select PCI
@@ -504,6 +519,7 @@ config ARCH_IOP33X
504 519 bool "IOP33x-based"
505 520 depends on MMU
506 521 select CPU_XSCALE
  522 + select NEED_MACH_IO_H
507 523 select NEED_RET_TO_USER
508 524 select PLAT_IOP
509 525 select PCI
@@ -517,6 +533,7 @@ config ARCH_IXP23XX
517 533 select CPU_XSC3
518 534 select PCI
519 535 select ARCH_USES_GETTIMEOFFSET
  536 + select NEED_MACH_IO_H
520 537 select NEED_MACH_MEMORY_H
521 538 help
522 539 Support for Intel's IXP23xx (XScale) family of processors.
@@ -527,6 +544,7 @@ config ARCH_IXP2000
527 544 select CPU_XSCALE
528 545 select PCI
529 546 select ARCH_USES_GETTIMEOFFSET
  547 + select NEED_MACH_IO_H
530 548 select NEED_MACH_MEMORY_H
531 549 help
532 550 Support for Intel's IXP2400/2800 (XScale) family of processors.
@@ -534,11 +552,13 @@ config ARCH_IXP2000
534 552 config ARCH_IXP4XX
535 553 bool "IXP4xx-based"
536 554 depends on MMU
  555 + select ARCH_HAS_DMA_SET_COHERENT_MASK
537 556 select CLKSRC_MMIO
538 557 select CPU_XSCALE
539 558 select GENERIC_GPIO
540 559 select GENERIC_CLOCKEVENTS
541 560 select MIGHT_HAVE_PCI
  561 + select NEED_MACH_IO_H
542 562 select DMABOUNCE if PCI
543 563 help
544 564 Support for Intel's IXP4XX (XScale) family of processors.
@@ -549,6 +569,7 @@ config ARCH_DOVE
549 569 select PCI
550 570 select ARCH_REQUIRE_GPIOLIB
551 571 select GENERIC_CLOCKEVENTS
  572 + select NEED_MACH_IO_H
552 573 select PLAT_ORION
553 574 help
554 575 Support for the Marvell Dove SoC 88AP510
@@ -559,6 +580,7 @@ config ARCH_KIRKWOOD
559 580 select PCI
560 581 select ARCH_REQUIRE_GPIOLIB
561 582 select GENERIC_CLOCKEVENTS
  583 + select NEED_MACH_IO_H
562 584 select PLAT_ORION
563 585 help
564 586 Support for the following Marvell Kirkwood series SoCs:
@@ -583,6 +605,7 @@ config ARCH_MV78XX0
583 605 select PCI
584 606 select ARCH_REQUIRE_GPIOLIB
585 607 select GENERIC_CLOCKEVENTS
  608 + select NEED_MACH_IO_H
586 609 select PLAT_ORION
587 610 help
588 611 Support for the following Marvell MV78xx0 series SoCs:
@@ -650,6 +673,7 @@ config ARCH_TEGRA
650 673 select HAVE_CLK
651 674 select HAVE_SMP
652 675 select MIGHT_HAVE_CACHE_L2X0
  676 + select NEED_MACH_IO_H if PCI
653 677 select ARCH_HAS_CPUFREQ
654 678 help
655 679 This enables support for NVIDIA Tegra based systems (Tegra APX,
@@ -741,6 +765,7 @@ config ARCH_RPC
741 765 select ARCH_SPARSEMEM_ENABLE
742 766 select ARCH_USES_GETTIMEOFFSET
743 767 select HAVE_IDE
  768 + select NEED_MACH_IO_H
744 769 select NEED_MACH_MEMORY_H
745 770 help
746 771 On the Acorn Risc-PC, Linux can support the internal IDE disk and
@@ -775,6 +800,7 @@ config ARCH_S3C24XX
775 800 select HAVE_S3C2410_I2C if I2C
776 801 select HAVE_S3C_RTC if RTC_CLASS
777 802 select HAVE_S3C2410_WATCHDOG if WATCHDOG
  803 + select NEED_MACH_IO_H
778 804 help
779 805 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
780 806 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
@@ -876,6 +902,7 @@ config ARCH_SHARK
876 902 select PCI
877 903 select ARCH_USES_GETTIMEOFFSET
878 904 select NEED_MACH_MEMORY_H
  905 + select NEED_MACH_IO_H
879 906 help
880 907 Support for the StrongARM based Digital DNARD machine, also known
881 908 as "Shark" (<http://www.shark-linux.de/shark.html>).
2  arch/arm/include/asm/assembler.h
@@ -23,6 +23,8 @@
23 23 #include <asm/ptrace.h>
24 24 #include <asm/domain.h>
25 25
  26 +#define IOMEM(x) (x)
  27 +
26 28 /*
27 29 * Endian independent macros for shifting bytes within registers.
28 30 */
71 arch/arm/include/asm/io.h
@@ -82,6 +82,11 @@ extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, uns
82 82 extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
83 83 extern void __iomem *__arm_ioremap_exec(unsigned long, size_t, bool cached);
84 84 extern void __iounmap(volatile void __iomem *addr);
  85 +extern void __arm_iounmap(volatile void __iomem *addr);
  86 +
  87 +extern void __iomem * (*arch_ioremap_caller)(unsigned long, size_t,
  88 + unsigned int, void *);
  89 +extern void (*arch_iounmap)(volatile void __iomem *);
85 90
86 91 /*
87 92 * Bad read/write accesses...
@@ -96,6 +101,8 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
96 101 return (void __iomem *)addr;
97 102 }
98 103
  104 +#define IOMEM(x) ((void __force __iomem *)(x))
  105 +
99 106 /* IO barriers */
100 107 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
101 108 #include <asm/barrier.h>
@@ -109,7 +116,11 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
109 116 /*
110 117 * Now, pick up the machine-defined IO definitions
111 118 */
  119 +#ifdef CONFIG_NEED_MACH_IO_H
112 120 #include <mach/io.h>
  121 +#else
  122 +#define __io(a) ({ (void)(a); __typesafe_io(0); })
  123 +#endif
113 124
114 125 /*
115 126 * This is the limit of PC card/PCI/ISA IO space, which is by default
@@ -211,18 +222,18 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
211 222 * Again, this are defined to perform little endian accesses. See the
212 223 * IO port primitives for more information.
213 224 */
214   -#ifdef __mem_pci
215   -#define readb_relaxed(c) ({ u8 __r = __raw_readb(__mem_pci(c)); __r; })
  225 +#ifndef readl
  226 +#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
216 227 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
217   - __raw_readw(__mem_pci(c))); __r; })
  228 + __raw_readw(c)); __r; })
218 229 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
219   - __raw_readl(__mem_pci(c))); __r; })
  230 + __raw_readl(c)); __r; })
220 231
221   -#define writeb_relaxed(v,c) ((void)__raw_writeb(v,__mem_pci(c)))
  232 +#define writeb_relaxed(v,c) ((void)__raw_writeb(v,c))
222 233 #define writew_relaxed(v,c) ((void)__raw_writew((__force u16) \
223   - cpu_to_le16(v),__mem_pci(c)))
  234 + cpu_to_le16(v),c))
224 235 #define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \
225   - cpu_to_le32(v),__mem_pci(c)))
  236 + cpu_to_le32(v),c))
226 237
227 238 #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
228 239 #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
@@ -232,30 +243,19 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
232 243 #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
233 244 #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
234 245
235   -#define readsb(p,d,l) __raw_readsb(__mem_pci(p),d,l)
236   -#define readsw(p,d,l) __raw_readsw(__mem_pci(p),d,l)
237   -#define readsl(p,d,l) __raw_readsl(__mem_pci(p),d,l)
238   -
239   -#define writesb(p,d,l) __raw_writesb(__mem_pci(p),d,l)
240   -#define writesw(p,d,l) __raw_writesw(__mem_pci(p),d,l)
241   -#define writesl(p,d,l) __raw_writesl(__mem_pci(p),d,l)
  246 +#define readsb(p,d,l) __raw_readsb(p,d,l)
  247 +#define readsw(p,d,l) __raw_readsw(p,d,l)
  248 +#define readsl(p,d,l) __raw_readsl(p,d,l)
242 249
243   -#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l))
244   -#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l))
245   -#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l))
  250 +#define writesb(p,d,l) __raw_writesb(p,d,l)
  251 +#define writesw(p,d,l) __raw_writesw(p,d,l)
  252 +#define writesl(p,d,l) __raw_writesl(p,d,l)
246 253
247   -#elif !defined(readb)
  254 +#define memset_io(c,v,l) _memset_io(c,(v),(l))
  255 +#define memcpy_fromio(a,c,l) _memcpy_fromio((a),c,(l))
  256 +#define memcpy_toio(c,a,l) _memcpy_toio(c,(a),(l))
248 257
249   -#define readb(c) (__readwrite_bug("readb"),0)
250   -#define readw(c) (__readwrite_bug("readw"),0)
251   -#define readl(c) (__readwrite_bug("readl"),0)
252   -#define writeb(v,c) __readwrite_bug("writeb")
253   -#define writew(v,c) __readwrite_bug("writew")
254   -#define writel(v,c) __readwrite_bug("writel")
255   -
256   -#define check_signature(io,sig,len) (0)
257   -
258   -#endif /* __mem_pci */
  258 +#endif /* readl */
259 259
260 260 /*
261 261 * ioremap and friends.
@@ -264,16 +264,11 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
264 264 * Documentation/io-mapping.txt.
265 265 *
266 266 */
267   -#ifndef __arch_ioremap
268   -#define __arch_ioremap __arm_ioremap
269   -#define __arch_iounmap __iounmap
270   -#endif
271   -
272   -#define ioremap(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE)
273   -#define ioremap_nocache(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE)
274   -#define ioremap_cached(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_CACHED)
275   -#define ioremap_wc(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_WC)
276   -#define iounmap __arch_iounmap
  267 +#define ioremap(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE)
  268 +#define ioremap_nocache(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE)
  269 +#define ioremap_cached(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_CACHED)
  270 +#define ioremap_wc(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_WC)
  271 +#define iounmap __arm_iounmap
277 272
278 273 /*
279 274 * io{read,write}{8,16,32} macros
1  arch/arm/kernel/debug.S
@@ -10,6 +10,7 @@
10 10 * 32-bit debugging code
11 11 */
12 12 #include <linux/linkage.h>
  13 +#include <asm/assembler.h>
13 14
14 15 .text
15 16
1  arch/arm/kernel/entry-armv.S
@@ -15,6 +15,7 @@
15 15 * that causes it to save wrong values... Be aware!
16 16 */
17 17
  18 +#include <asm/assembler.h>
18 19 #include <asm/memory.h>
19 20 #include <asm/glue-df.h>
20 21 #include <asm/glue-pf.h>
31 arch/arm/mach-at91/include/mach/io.h
... ... @@ -1,31 +0,0 @@
1   -/*
2   - * arch/arm/mach-at91/include/mach/io.h
3   - *
4   - * Copyright (C) 2003 SAN People
5   - *
6   - * This program is free software; you can redistribute it and/or modify
7   - * it under the terms of the GNU General Public License as published by
8   - * the Free Software Foundation; either version 2 of the License, or
9   - * (at your option) any later version.
10   - *
11   - * This program is distributed in the hope that it will be useful,
12   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
13   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14   - * GNU General Public License for more details.
15   - *
16   - * You should have received a copy of the GNU General Public License
17   - * along with this program; if not, write to the Free Software
18   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19   - */
20   -
21   -#ifndef __ASM_ARCH_IO_H
22   -#define __ASM_ARCH_IO_H
23   -
24   -#include <mach/hardware.h>
25   -
26   -#define IO_SPACE_LIMIT 0xFFFFFFFF
27   -
28   -#define __io(a) __typesafe_io(a)
29   -#define __mem_pci(a) (a)
30   -
31   -#endif
1  arch/arm/mach-at91/include/mach/uncompress.h
@@ -23,6 +23,7 @@
23 23
24 24 #include <linux/io.h>
25 25 #include <linux/atmel_serial.h>
  26 +#include <mach/hardware.h>
26 27
27 28 #if defined(CONFIG_AT91_EARLY_DBGU0)
28 29 #define UART_OFFSET AT91_BASE_DBGU0
33 arch/arm/mach-bcmring/include/mach/io.h
... ... @@ -1,33 +0,0 @@
1   -/*
2   - *
3   - * Copyright (C) 1999 ARM Limited
4   - *
5   - * This program is free software; you can redistribute it and/or modify
6   - * it under the terms of the GNU General Public License as published by
7   - * the Free Software Foundation; either version 2 of the License, or
8   - * (at your option) any later version.
9   - *
10   - * This program is distributed in the hope that it will be useful,
11   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
12   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13   - * GNU General Public License for more details.
14   - *
15   - * You should have received a copy of the GNU General Public License
16   - * along with this program; if not, write to the Free Software
17   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18   - */
19   -#ifndef __ASM_ARM_ARCH_IO_H
20   -#define __ASM_ARM_ARCH_IO_H
21   -
22   -#include <mach/hardware.h>
23   -
24   -#define IO_SPACE_LIMIT 0xffffffff
25   -
26   -/*
27   - * We don't actually have real ISA nor PCI buses, but there is so many
28   - * drivers out there that might just work if we fake them...
29   - */
30   -#define __io(a) __typesafe_io(a)
31   -#define __mem_pci(a) (a)
32   -
33   -#endif
36 arch/arm/mach-clps711x/include/mach/io.h
... ... @@ -1,36 +0,0 @@
1   -/*
2   - * arch/arm/mach-clps711x/include/mach/io.h
3   - *
4   - * Copyright (C) 1999 ARM Limited
5   - *
6   - * This program is free software; you can redistribute it and/or modify
7   - * it under the terms of the GNU General Public License as published by
8   - * the Free Software Foundation; either version 2 of the License, or
9   - * (at your option) any later version.
10   - *
11   - * This program is distributed in the hope that it will be useful,
12   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
13   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14   - * GNU General Public License for more details.
15   - *
16   - * You should have received a copy of the GNU General Public License
17   - * along with this program; if not, write to the Free Software
18   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19   - */
20   -#ifndef __ASM_ARM_ARCH_IO_H
21   -#define __ASM_ARM_ARCH_IO_H
22   -
23   -#define IO_SPACE_LIMIT 0xffffffff
24   -
25   -#define __io(a) __typesafe_io(a)
26   -#define __mem_pci(a) (a)
27   -
28   -/*
29   - * We don't support ins[lb]/outs[lb]. Make them fault.
30   - */
31   -#define __raw_readsb(p,d,l) do { *(int *)0 = 0; } while (0)
32   -#define __raw_readsl(p,d,l) do { *(int *)0 = 0; } while (0)
33   -#define __raw_writesb(p,d,l) do { *(int *)0 = 0; } while (0)
34   -#define __raw_writesl(p,d,l) do { *(int *)0 = 0; } while (0)
35   -
36   -#endif
1  arch/arm/mach-clps711x/include/mach/uncompress.h
@@ -17,7 +17,6 @@
17 17 * along with this program; if not, write to the Free Software
18 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 19 */
20   -#include <mach/io.h>
21 20 #include <mach/hardware.h>
22 21 #include <asm/hardware/clps7111.h>
23 22
8 arch/arm/mach-cns3xxx/core.c
@@ -72,13 +72,13 @@ void __init cns3xxx_map_io(void)
72 72 /* used by entry-macro.S */
73 73 void __init cns3xxx_init_irq(void)
74 74 {
75   - gic_init(0, 29, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
76   - __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
  75 + gic_init(0, 29, IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
  76 + IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
77 77 }
78 78
79 79 void cns3xxx_power_off(void)
80 80 {
81   - u32 __iomem *pm_base = __io(CNS3XXX_PM_BASE_VIRT);
  81 + u32 __iomem *pm_base = IOMEM(CNS3XXX_PM_BASE_VIRT);
82 82 u32 clkctrl;
83 83
84 84 printk(KERN_INFO "powering system down...\n");
@@ -237,7 +237,7 @@ static void __init __cns3xxx_timer_init(unsigned int timer_irq)
237 237
238 238 static void __init cns3xxx_timer_init(void)
239 239 {
240   - cns3xxx_tmr1 = __io(CNS3XXX_TIMER1_2_3_BASE_VIRT);
  240 + cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT);
241 241
242 242 __cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0);
243 243 }
2  arch/arm/mach-cns3xxx/devices.c
@@ -98,7 +98,7 @@ static struct platform_device cns3xxx_sdhci_pdev = {
98 98
99 99 void __init cns3xxx_sdhci_init(void)
100 100 {
101   - u32 __iomem *gpioa = __io(CNS3XXX_MISC_BASE_VIRT + 0x0014);
  101 + u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
102 102 u32 gpioa_pins = __raw_readl(gpioa);
103 103
104 104 /* MMC/SD pins share with GPIOA */
17 arch/arm/mach-cns3xxx/include/mach/io.h
... ... @@ -1,17 +0,0 @@
1   -/*
2   - * Copyright 2008 Cavium Networks
3   - * Copyright 2003 ARM Limited
4   - *
5   - * This file is free software; you can redistribute it and/or modify
6   - * it under the terms of the GNU General Public License, Version 2, as
7   - * published by the Free Software Foundation.
8   - */
9   -#ifndef __MACH_IO_H
10   -#define __MACH_IO_H
11   -
12   -#define IO_SPACE_LIMIT 0xffffffff
13   -
14   -#define __io(a) __typesafe_io(a)
15   -#define __mem_pci(a) (a)
16   -
17   -#endif
1  arch/arm/mach-davinci/include/mach/entry-macro.S
@@ -8,7 +8,6 @@
8 8 * is licensed "as is" without any warranty of any kind, whether express
9 9 * or implied.
10 10 */
11   -#include <mach/io.h>
12 11 #include <mach/irqs.h>
13 12
14 13 .macro get_irqnr_preamble, base, tmp
6 arch/arm/mach-davinci/include/mach/hardware.h
@@ -30,10 +30,4 @@
30 30 #define __IO_ADDRESS(x) ((x) + IO_OFFSET)
31 31 #define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))
32 32
33   -#ifdef __ASSEMBLER__
34   -#define IOMEM(x) x
35   -#else
36   -#define IOMEM(x) ((void __force __iomem *)(x))
37   -#endif
38   -
39 33 #endif /* __ASM_ARCH_HARDWARE_H */
24 arch/arm/mach-davinci/include/mach/io.h
... ... @@ -1,24 +0,0 @@
1   -/*
2   - * DaVinci IO address definitions
3   - *
4   - * Copied from include/asm/arm/arch-omap/io.h
5   - *
6   - * 2007 (c) MontaVista Software, Inc. This file is licensed under
7   - * the terms of the GNU General Public License version 2. This program
8   - * is licensed "as is" without any warranty of any kind, whether express
9   - * or implied.
10   - */
11   -#ifndef __ASM_ARCH_IO_H
12   -#define __ASM_ARCH_IO_H
13   -
14   -#define IO_SPACE_LIMIT 0xffffffff
15   -
16   -/*
17   - * We don't actually have real ISA nor PCI buses, but there is so many
18   - * drivers out there that might just work if we fake them...
19   - */
20   -#define __io(a) __typesafe_io(a)
21   -#define __mem_pci(a) (a)
22   -#define __mem_isa(a) (a)
23   -
24   -#endif /* __ASM_ARCH_IO_H */
2  arch/arm/mach-davinci/include/mach/uncompress.h
@@ -25,6 +25,8 @@
25 25
26 26 #include <mach/serial.h>
27 27
  28 +#define IOMEM(x) ((void __force __iomem *)(x))
  29 +
28 30 u32 *uart;
29 31
30 32 /* PORT_16C550A, in polled non-fifo mode */
1  arch/arm/mach-dove/addr-map.c
@@ -14,6 +14,7 @@
14 14 #include <linux/io.h>
15 15 #include <asm/mach/arch.h>
16 16 #include <asm/setup.h>
  17 +#include <mach/dove.h>
17 18 #include <plat/addr-map.h>
18 19 #include "common.h"
19 20
1  arch/arm/mach-dove/include/mach/io.h
@@ -15,6 +15,5 @@
15 15
16 16 #define __io(a) ((void __iomem *)(((a) - DOVE_PCIE0_IO_BUS_BASE) + \
17 17 DOVE_PCIE0_IO_VIRT_BASE))
18   -#define __mem_pci(a) (a)
19 18
20 19 #endif
15 arch/arm/mach-ebsa110/core.c
@@ -116,6 +116,20 @@ static void __init ebsa110_map_io(void)
116 116 iotable_init(ebsa110_io_desc, ARRAY_SIZE(ebsa110_io_desc));
117 117 }
118 118
  119 +static void __iomem *ebsa110_ioremap_caller(unsigned long cookie, size_t size,
  120 + unsigned int flags, void *caller)
  121 +{
  122 + return (void __iomem *)cookie;
  123 +}
  124 +
  125 +static void ebsa110_iounmap(volatile void __iomem *io_addr)
  126 +{}
  127 +
  128 +static void __init ebsa110_init_early(void)
  129 +{
  130 + arch_ioremap_caller = ebsa110_ioremap_caller;
  131 + arch_iounmap = ebsa110_iounmap;
  132 +}
119 133
120 134 #define PIT_CTRL (PIT_BASE + 0x0d)
121 135 #define PIT_T2 (PIT_BASE + 0x09)
@@ -312,6 +326,7 @@ MACHINE_START(EBSA110, "EBSA110")
312 326 .reserve_lp2 = 1,
313 327 .restart_mode = 's',
314 328 .map_io = ebsa110_map_io,
  329 + .init_early = ebsa110_init_early,
315 330 .init_irq = ebsa110_init_irq,
316 331 .timer = &ebsa110_timer,
317 332 .restart = ebsa110_restart,
9 arch/arm/mach-ebsa110/include/mach/io.h
@@ -62,15 +62,6 @@ void __writel(u32 val, void __iomem *addr);
62 62 #define writew(v,b) __writew(v,b)
63 63 #define writel(v,b) __writel(v,b)
64 64
65   -static inline void __iomem *__arch_ioremap(unsigned long cookie, size_t size,
66   - unsigned int flags)
67   -{
68   - return (void __iomem *)cookie;
69   -}
70   -
71   -#define __arch_ioremap __arch_ioremap
72   -#define __arch_iounmap(cookie) do { } while (0)
73   -
74 65 extern void insb(unsigned int port, void *buf, int sz);
75 66 extern void insw(unsigned int port, void *buf, int sz);
76 67 extern void insl(unsigned int port, void *buf, int sz);
22 arch/arm/mach-ep93xx/include/mach/io.h
... ... @@ -1,22 +0,0 @@
1   -/*
2   - * arch/arm/mach-ep93xx/include/mach/io.h
3   - */
4   -
5   -#ifndef __ASM_MACH_IO_H
6   -#define __ASM_MACH_IO_H
7   -
8   -#define IO_SPACE_LIMIT 0xffffffff
9   -
10   -#define __io(p) __typesafe_io(p)
11   -#define __mem_pci(p) (p)
12   -
13   -/*
14   - * A typesafe __io() variation for variable initialisers
15   - */
16   -#ifdef __ASSEMBLER__
17   -#define IOMEM(p) p
18   -#else
19   -#define IOMEM(p) ((void __iomem __force *)(p))
20   -#endif
21   -
22   -#endif /* __ASM_MACH_IO_H */
26 arch/arm/mach-exynos/include/mach/io.h
... ... @@ -1,26 +0,0 @@
1   -/* linux/arch/arm/mach-exynos4/include/mach/io.h
2   - *
3   - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4   - * http://www.samsung.com
5   - *
6   - * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org>
7   - *
8   - * Based on arch/arm/mach-s5p6442/include/mach/io.h
9   - *
10   - * Default IO routines for EXYNOS4
11   - *
12   - * This program is free software; you can redistribute it and/or modify
13   - * it under the terms of the GNU General Public License version 2 as
14   - * published by the Free Software Foundation.
15   -*/
16   -
17   -#ifndef __ASM_ARM_ARCH_IO_H
18   -#define __ASM_ARM_ARCH_IO_H __FILE__
19   -
20   -/* No current ISA/PCI bus support. */
21   -#define __io(a) __typesafe_io(a)
22   -#define __mem_pci(a) (a)
23   -
24   -#define IO_SPACE_LIMIT (0xFFFFFFFF)
25   -
26   -#endif /* __ASM_ARM_ARCH_IO_H */
13 arch/arm/mach-footbridge/include/mach/io.h
@@ -27,18 +27,5 @@
27 27 * Translation of various region addresses to virtual addresses
28 28 */
29 29 #define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
30   -#if 1
31   -#define __mem_pci(a) (a)
32   -#else
33   -
34   -static inline void __iomem *___mem_pci(void __iomem *p)
35   -{
36   - unsigned long a = (unsigned long)p;
37   - BUG_ON(a <= 0xc0000000 || a >= 0xe0000000);
38   - return p;
39   -}
40   -
41   -#define __mem_pci(a) ___mem_pci(a)
42   -#endif
43 30
44 31 #endif
18 arch/arm/mach-gemini/include/mach/io.h
... ... @@ -1,18 +0,0 @@
1   -/*
2   - * Copyright (C) 2001-2006 Storlink, Corp.
3   - * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
4   - *
5   - * This program is free software; you can redistribute it and/or modify
6   - * it under the terms of the GNU General Public License as published by
7   - * the Free Software Foundation; either version 2 of the License, or
8   - * (at your option) any later version.
9   - */
10   -#ifndef __MACH_IO_H
11   -#define __MACH_IO_H
12   -
13   -#define IO_SPACE_LIMIT 0xffffffff
14   -
15   -#define __io(a) __typesafe_io(a)
16   -#define __mem_pci(a) (a)
17   -
18   -#endif /* __MACH_IO_H */
22 arch/arm/mach-h720x/include/mach/io.h
... ... @@ -1,22 +0,0 @@
1   -/*
2   - * arch/arm/mach-h720x/include/mach/io.h
3   - *
4   - * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
5   - *
6   - * Changelog:
7   - *
8   - * 09-19-2001 JJKIM
9   - * Created from arch/arm/mach-l7200/include/mach/io.h
10   - *
11   - * 03-27-2003 Robert Schwebel <r.schwebel@pengutronix.de>:
12   - * re-unified header files for h720x
13   - */
14   -#ifndef __ASM_ARM_ARCH_IO_H
15   -#define __ASM_ARM_ARCH_IO_H
16   -
17   -#define IO_SPACE_LIMIT 0xffffffff
18   -
19   -#define __io(a) __typesafe_io(a)
20   -#define __mem_pci(a) (a)
21   -
22   -#endif
7 arch/arm/mach-highbank/include/mach/io.h
... ... @@ -1,7 +0,0 @@
1   -#ifndef __MACH_IO_H
2   -#define __MACH_IO_H
3   -
4   -#define __io(a) ({ (void)(a); __typesafe_io(0); })
5   -#define __mem_pci(a) (a)
6   -
7   -#endif
10 arch/arm/mach-imx/mm-imx3.c
@@ -61,8 +61,8 @@ static void imx3_idle(void)
61 61 : "=r" (reg));
62 62 }
63 63
64   -static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
65   - unsigned int mtype)
  64 +static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
  65 + unsigned int mtype, void *caller)
66 66 {
67 67 if (mtype == MT_DEVICE) {
68 68 /*
@@ -75,7 +75,7 @@ static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
75 75 mtype = MT_DEVICE_NONSHARED;
76 76 }
77 77
78   - return __arm_ioremap(phys_addr, size, mtype);
  78 + return __arm_ioremap_caller(phys_addr, size, mtype, caller);
79 79 }
80 80
81 81 void __init imx3_init_l2x0(void)
@@ -134,7 +134,7 @@ void __init imx31_init_early(void)
134 134 {
135 135 mxc_set_cpu_type(MXC_CPU_MX31);
136 136 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
137   - imx_ioremap = imx3_ioremap;
  137 + arch_ioremap_caller = imx3_ioremap_caller;
138 138 arm_pm_idle = imx3_idle;
139 139 }
140 140
@@ -208,7 +208,7 @@ void __init imx35_init_early(void)
208 208 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
209 209 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
210 210 arm_pm_idle = imx3_idle;
211   - imx_ioremap = imx3_ioremap;
  211 + arch_ioremap_caller = imx3_ioremap_caller;
212 212 }
213 213
214 214 void __init mx35_init_irq(void)
1  arch/arm/mach-integrator/include/mach/io.h
@@ -29,6 +29,5 @@
29 29 #define PCI_IO_VADDR 0xee000000
30 30
31 31 #define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a)))
32   -#define __mem_pci(a) (a)
33 32
34 33 #endif
13 arch/arm/mach-iop13xx/include/mach/io.h
@@ -22,20 +22,7 @@
22 22 #define IO_SPACE_LIMIT 0xffffffff
23 23
24 24 #define __io(a) __iop13xx_io(a)
25   -#define __mem_pci(a) (a)
26   -#define __mem_isa(a) (a)
27 25
28 26 extern void __iomem * __iop13xx_io(unsigned long io_addr);
29   -extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size,
30   - unsigned int mtype);
31   -extern void __iop13xx_iounmap(void __iomem *addr);
32   -
33   -extern u32 iop13xx_atue_mem_base;
34   -extern u32 iop13xx_atux_mem_base;
35   -extern size_t iop13xx_atue_mem_size;
36   -extern size_t iop13xx_atux_mem_size;
37   -
38   -#define __arch_ioremap __iop13xx_ioremap
39   -#define __arch_iounmap __iop13xx_iounmap
40 27
41 28 #endif
1  arch/arm/mach-iop13xx/include/mach/iop13xx.h
@@ -5,6 +5,7 @@
5 5 /* The ATU offsets can change based on the strapping */
6 6 extern u32 iop13xx_atux_pmmr_offset;
7 7 extern u32 iop13xx_atue_pmmr_offset;
  8 +void iop13xx_init_early(void);
8 9 void iop13xx_init_irq(void);
9 10 void iop13xx_map_io(void);
10 11 void iop13xx_platform_init(void);
20 arch/arm/mach-iop13xx/io.c
@@ -21,6 +21,8 @@
21 21 #include <linux/io.h>
22 22 #include <mach/hardware.h>
23 23
  24 +#include "pci.h"
  25 +
24 26 void * __iomem __iop13xx_io(unsigned long io_addr)
25 27 {
26 28 void __iomem * io_virt;
@@ -40,8 +42,8 @@ void * __iomem __iop13xx_io(unsigned long io_addr)
40 42 }
41 43 EXPORT_SYMBOL(__iop13xx_io);
42 44
43   -void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
44   - unsigned int mtype)
  45 +static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
  46 + size_t size, unsigned int mtype, void *caller)
45 47 {
46 48 void __iomem * retval;
47 49
@@ -76,17 +78,14 @@ void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
76 78 break;
77 79 default:
78 80 retval = __arm_ioremap_caller(cookie, size, mtype,
79   - __builtin_return_address(0));
  81 + caller);
80 82 }
81 83
82 84 return retval;
83 85 }
84   -EXPORT_SYMBOL(__iop13xx_ioremap);
85 86
86   -void __iop13xx_iounmap(void __iomem *addr)
  87 +static void __iop13xx_iounmap(volatile void __iomem *addr)
87 88 {
88   - extern void __iounmap(volatile void __iomem *addr);
89   -
90 89 if (iop13xx_atue_mem_base)
91 90 if (addr >= (void __iomem *) iop13xx_atue_mem_base &&
92 91 addr < (void __iomem *) (iop13xx_atue_mem_base +
@@ -110,4 +109,9 @@ void __iop13xx_iounmap(void __iomem *addr)
110 109 skip:
111 110 return;
112 111 }
113   -EXPORT_SYMBOL(__iop13xx_iounmap);
  112 +
  113 +void __init iop13xx_init_early(void)
  114 +{
  115 + arch_ioremap_caller = __iop13xx_ioremap_caller;
  116 + arch_iounmap = __iop13xx_iounmap;
  117 +}
1  arch/arm/mach-iop13xx/iq81340mc.c
@@ -92,6 +92,7 @@ static struct sys_timer iq81340mc_timer = {
92 92 MACHINE_START(IQ81340MC, "Intel IQ81340MC")
93 93 /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
94 94 .atag_offset = 0x100,
  95 + .init_early = iop13xx_init_early,
95 96 .map_io = iop13xx_map_io,
96 97 .init_irq = iop13xx_init_irq,
97 98 .timer = &iq81340mc_timer,
1  arch/arm/mach-iop13xx/iq81340sc.c
@@ -94,6 +94,7 @@ static struct sys_timer iq81340sc_timer = {
94 94 MACHINE_START(IQ81340SC, "Intel IQ81340SC")
95 95 /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
96 96 .atag_offset = 0x100,
  97 + .init_early = iop13xx_init_early,
97 98 .map_io = iop13xx_map_io,
98 99 .init_irq = iop13xx_init_irq,
99 100 .timer = &iq81340sc_timer,
6 arch/arm/mach-iop13xx/pci.h
... ... @@ -0,0 +1,6 @@
  1 +#include <linux/types.h>
  2 +
  3 +extern u32 iop13xx_atue_mem_base;
  4 +extern u32 iop13xx_atux_mem_base;
  5 +extern size_t iop13xx_atue_mem_size;
  6 +extern size_t iop13xx_atux_mem_size;
1  arch/arm/mach-iop32x/include/mach/io.h
@@ -15,6 +15,5 @@
15 15
16 16 #define IO_SPACE_LIMIT 0xffffffff
17 17 #define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
18   -#define __mem_pci(a) (a)
19 18
20 19 #endif
1  arch/arm/mach-iop33x/include/mach/io.h
@@ -15,6 +15,5 @@
15 15
16 16 #define IO_SPACE_LIMIT 0xffffffff
17 17 #define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
18   -#define __mem_pci(a) (a)
19 18
20 19 #endif
1  arch/arm/mach-ixp2000/include/mach/io.h
@@ -18,7 +18,6 @@
18 18 #include <mach/hardware.h>
19 19
20 20 #define IO_SPACE_LIMIT 0xffffffff
21   -#define __mem_pci(a) (a)
22 21
23 22 /*
24 23 * The A? revisions of the IXP2000s assert byte lanes for PCI I/O
1  arch/arm/mach-ixp23xx/include/mach/io.h
@@ -18,6 +18,5 @@
18 18 #define IO_SPACE_LIMIT 0xffffffff
19 19
20 20 #define __io(p) ((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT))
21   -#define __mem_pci(a) (a)
22 21
23 22 #endif
2  arch/arm/mach-ixp4xx/avila-setup.c
@@ -165,6 +165,7 @@ static void __init avila_init(void)
165 165 MACHINE_START(AVILA, "Gateworks Avila Network Platform")
166 166 /* Maintainer: Deepak Saxena <dsaxena@plexity.net> */
167 167 .map_io = ixp4xx_map_io,
  168 + .init_early = ixp4xx_init_early,
168 169 .init_irq = ixp4xx_init_irq,
169 170 .timer = &ixp4xx_timer,
170 171 .atag_offset = 0x100,
@@ -184,6 +185,7 @@ MACHINE_END
184 185 MACHINE_START(LOFT, "Giant Shoulder Inc Loft board")
185 186 /* Maintainer: Tom Billman <kernel@giantshoulderinc.com> */
186 187 .map_io = ixp4xx_map_io,
  188 + .init_early = ixp4xx_init_early,
187 189 .init_irq = ixp4xx_init_irq,
188 190 .timer = &ixp4xx_timer,
189 191 .atag_offset = 0x100,
33 arch/arm/mach-ixp4xx/common.c
@@ -31,6 +31,7 @@
31 31
32 32 #include <mach/udc.h>
33 33 #include <mach/hardware.h>
  34 +#include <mach/io.h>
34 35 #include <asm/uaccess.h>
35 36 #include <asm/pgtable.h>
36 37 #include <asm/page.h>
@@ -517,3 +518,35 @@ void ixp4xx_restart(char mode, const char *cmd)
517 518 *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
518 519 }
519 520 }
  521 +
  522 +#ifdef CONFIG_IXP4XX_INDIRECT_PCI
  523 +/*
  524 + * In the case of using indirect PCI, we simply return the actual PCI
  525 + * address and our read/write implementation use that to drive the
  526 + * access registers. If something outside of PCI is ioremap'd, we
  527 + * fallback to the default.
  528 + */
  529 +
  530 +static void __iomem *ixp4xx_ioremap_caller(unsigned long addr, size_t size,
  531 + unsigned int mtype, void *caller)
  532 +{
  533 + if (!is_pci_memory(addr))
  534 + return __arm_ioremap_caller(addr, size, mtype, caller);
  535 +
  536 + return (void __iomem *)addr;
  537 +}
  538 +
  539 +static void ixp4xx_iounmap(void __iomem *addr)
  540 +{
  541 + if (!is_pci_memory((__force u32)addr))
  542 + __iounmap(addr);
  543 +}
  544 +
  545 +void __init ixp4xx_init_early(void)
  546 +{
  547 + arch_ioremap_caller = ixp4xx_ioremap_caller;
  548 + arch_iounmap = ixp4xx_iounmap;
  549 +}
  550 +#else
  551 +void __init ixp4xx_init_early(void) {}
  552 +#endif
2  arch/arm/mach-ixp4xx/coyote-setup.c
@@ -110,6 +110,7 @@ static void __init coyote_init(void)
110 110 MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote")
111 111 /* Maintainer: MontaVista Software, Inc. */
112 112 .map_io = ixp4xx_map_io,
  113 + .init_early = ixp4xx_init_early,
113 114 .init_irq = ixp4xx_init_irq,
114 115 .timer = &ixp4xx_timer,
115 116 .atag_offset = 0x100,
@@ -129,6 +130,7 @@ MACHINE_END
129 130 MACHINE_START(IXDPG425, "Intel IXDPG425")
130 131 /* Maintainer: MontaVista Software, Inc. */
131 132 .map_io = ixp4xx_map_io,
  133 + .init_early = ixp4xx_init_early,
132 134 .init_irq = ixp4xx_init_irq,
133 135 .timer = &ixp4xx_timer,
134 136 .atag_offset = 0x100,
1  arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -280,6 +280,7 @@ MACHINE_START(DSMG600, "D-Link DSM-G600 RevA")
280 280 /* Maintainer: www.nslu2-linux.org */
281 281 .atag_offset = 0x100,
282 282 .map_io = ixp4xx_map_io,
  283 + .init_early = ixp4xx_init_early,
283 284 .init_irq = ixp4xx_init_irq,
284 285 .timer = &dsmg600_timer,
285 286 .init_machine = dsmg600_init,
1  arch/arm/mach-ixp4xx/fsg-setup.c
@@ -270,6 +270,7 @@ static void __init fsg_init(void)
270 270 MACHINE_START(FSG, "Freecom FSG-3")
271 271 /* Maintainer: www.nslu2-linux.org */
272 272 .map_io = ixp4xx_map_io,
  273 + .init_early = ixp4xx_init_early,
273 274 .init_irq = ixp4xx_init_irq,
274 275 .timer = &ixp4xx_timer,
275 276 .atag_offset = 0x100,
1  arch/arm/mach-ixp4xx/gateway7001-setup.c
@@ -97,6 +97,7 @@ static void __init gateway7001_init(void)
97 97 MACHINE_START(GATEWAY7001, "Gateway 7001 AP")