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Merge tag 'metag-v3.9-rc1-v4' of git://git.kernel.org/pub/scm/linux/k…

…ernel/git/jhogan/metag

Pull new ImgTec Meta architecture from James Hogan:
 "This adds core architecture support for Imagination's Meta processor
  cores, followed by some later miscellaneous arch/metag cleanups and
  fixes which I kept separate to ease review:

   - Support for basic Meta 1 (ATP) and Meta 2 (HTP) core architecture
   - A few fixes all over, particularly for symbol prefixes
   - A few privilege protection fixes
   - Several cleanups (setup.c includes, split out a lot of
     metag_ksyms.c)
   - Fix some missing exports
   - Convert hugetlb to use vm_unmapped_area()
   - Copy device tree to non-init memory
   - Provide dma_get_sgtable()"

* tag 'metag-v3.9-rc1-v4' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/metag: (61 commits)
  metag: Provide dma_get_sgtable()
  metag: prom.h: remove declaration of metag_dt_memblock_reserve()
  metag: copy devicetree to non-init memory
  metag: cleanup metag_ksyms.c includes
  metag: move mm/init.c exports out of metag_ksyms.c
  metag: move usercopy.c exports out of metag_ksyms.c
  metag: move setup.c exports out of metag_ksyms.c
  metag: move kick.c exports out of metag_ksyms.c
  metag: move traps.c exports out of metag_ksyms.c
  metag: move irq enable out of irqflags.h on SMP
  genksyms: fix metag symbol prefix on crc symbols
  metag: hugetlb: convert to vm_unmapped_area()
  metag: export clear_page and copy_page
  metag: export metag_code_cache_flush_all
  metag: protect more non-MMU memory regions
  metag: make TXPRIVEXT bits explicit
  metag: kernel/setup.c: sort includes
  perf: Enable building perf tools for Meta
  metag: add boot time LNKGET/LNKSET check
  metag: add __init to metag_cache_probe()
  ...
  • Loading branch information...
torvalds committed Mar 3, 2013
2 parents 529e5fb + c60ac31 commit 8fd5e7a2d9574b3cac1c9264ad1aed3b613ed6fe
Showing with 26,934 additions and 8 deletions.
  1. +2 −0 Documentation/00-INDEX
  2. +82 −0 Documentation/devicetree/bindings/metag/meta-intc.txt
  3. +4 −0 Documentation/kernel-parameters.txt
  4. +4 −0 Documentation/metag/00-INDEX
  5. +256 −0 Documentation/metag/kernel-ABI.txt
  6. +12 −0 MAINTAINERS
  7. +16 −0 arch/Kconfig
  8. +290 −0 arch/metag/Kconfig
  9. +40 −0 arch/metag/Kconfig.debug
  10. +55 −0 arch/metag/Kconfig.soc
  11. +87 −0 arch/metag/Makefile
  12. +4 −0 arch/metag/boot/.gitignore
  13. +68 −0 arch/metag/boot/Makefile
  14. +16 −0 arch/metag/boot/dts/Makefile
  15. +10 −0 arch/metag/boot/dts/skeleton.dts
  16. +14 −0 arch/metag/boot/dts/skeleton.dtsi
  17. +40 −0 arch/metag/configs/meta1_defconfig
  18. +41 −0 arch/metag/configs/meta2_defconfig
  19. +42 −0 arch/metag/configs/meta2_smp_defconfig
  20. +54 −0 arch/metag/include/asm/Kbuild
  21. +53 −0 arch/metag/include/asm/atomic.h
  22. +234 −0 arch/metag/include/asm/atomic_lnkget.h
  23. +160 −0 arch/metag/include/asm/atomic_lock1.h
  24. +85 −0 arch/metag/include/asm/barrier.h
  25. +132 −0 arch/metag/include/asm/bitops.h
  26. +12 −0 arch/metag/include/asm/bug.h
  27. +23 −0 arch/metag/include/asm/cache.h
  28. +250 −0 arch/metag/include/asm/cacheflush.h
  29. +42 −0 arch/metag/include/asm/cachepart.h
  30. +92 −0 arch/metag/include/asm/checksum.h
  31. +51 −0 arch/metag/include/asm/clock.h
  32. +65 −0 arch/metag/include/asm/cmpxchg.h
  33. +42 −0 arch/metag/include/asm/cmpxchg_irq.h
  34. +86 −0 arch/metag/include/asm/cmpxchg_lnkget.h
  35. +48 −0 arch/metag/include/asm/cmpxchg_lock1.h
  36. +35 −0 arch/metag/include/asm/core_reg.h
  37. +14 −0 arch/metag/include/asm/cpu.h
  38. +43 −0 arch/metag/include/asm/da.h
  39. +29 −0 arch/metag/include/asm/delay.h
  40. +12 −0 arch/metag/include/asm/div64.h
  41. +190 −0 arch/metag/include/asm/dma-mapping.h
  42. +128 −0 arch/metag/include/asm/elf.h
  43. +99 −0 arch/metag/include/asm/fixmap.h
  44. +23 −0 arch/metag/include/asm/ftrace.h
  45. +100 −0 arch/metag/include/asm/global_lock.h
  46. +4 −0 arch/metag/include/asm/gpio.h
  47. +62 −0 arch/metag/include/asm/highmem.h
  48. +86 −0 arch/metag/include/asm/hugetlb.h
  49. +40 −0 arch/metag/include/asm/hwthread.h
  50. +165 −0 arch/metag/include/asm/io.h
  51. +32 −0 arch/metag/include/asm/irq.h
  52. +93 −0 arch/metag/include/asm/irqflags.h
  53. +258 −0 arch/metag/include/asm/l2cache.h
  54. +7 −0 arch/metag/include/asm/linkage.h
  55. +86 −0 arch/metag/include/asm/mach/arch.h
  56. +81 −0 arch/metag/include/asm/metag_isa.h
  57. +1,106 −0 arch/metag/include/asm/metag_mem.h
  58. +1,184 −0 arch/metag/include/asm/metag_regs.h
  59. +11 −0 arch/metag/include/asm/mman.h
  60. +77 −0 arch/metag/include/asm/mmu.h
  61. +113 −0 arch/metag/include/asm/mmu_context.h
  62. +42 −0 arch/metag/include/asm/mmzone.h
  63. +37 −0 arch/metag/include/asm/module.h
  64. +128 −0 arch/metag/include/asm/page.h
  65. +4 −0 arch/metag/include/asm/perf_event.h
  66. +79 −0 arch/metag/include/asm/pgalloc.h
  67. +370 −0 arch/metag/include/asm/pgtable.h
  68. +202 −0 arch/metag/include/asm/processor.h
  69. +23 −0 arch/metag/include/asm/prom.h
  70. +60 −0 arch/metag/include/asm/ptrace.h
  71. +8 −0 arch/metag/include/asm/setup.h
  72. +29 −0 arch/metag/include/asm/smp.h
  73. +13 −0 arch/metag/include/asm/sparsemem.h
  74. +22 −0 arch/metag/include/asm/spinlock.h
  75. +249 −0 arch/metag/include/asm/spinlock_lnkget.h
  76. +184 −0 arch/metag/include/asm/spinlock_lock1.h
  77. +20 −0 arch/metag/include/asm/spinlock_types.h
  78. +20 −0 arch/metag/include/asm/stacktrace.h
  79. +13 −0 arch/metag/include/asm/string.h
  80. +21 −0 arch/metag/include/asm/switch.h
  81. +104 −0 arch/metag/include/asm/syscall.h
  82. +39 −0 arch/metag/include/asm/syscalls.h
  83. +1,425 −0 arch/metag/include/asm/tbx.h
  84. +30 −0 arch/metag/include/asm/tcm.h
  85. +155 −0 arch/metag/include/asm/thread_info.h
  86. +36 −0 arch/metag/include/asm/tlb.h
  87. +77 −0 arch/metag/include/asm/tlbflush.h
  88. +53 −0 arch/metag/include/asm/topology.h
  89. +48 −0 arch/metag/include/asm/traps.h
  90. +241 −0 arch/metag/include/asm/uaccess.h
  91. +12 −0 arch/metag/include/asm/unistd.h
  92. +44 −0 arch/metag/include/asm/user_gateway.h
  93. +13 −0 arch/metag/include/uapi/asm/Kbuild
  94. +1 −0 arch/metag/include/uapi/asm/byteorder.h
  95. +113 −0 arch/metag/include/uapi/asm/ptrace.h
  96. +7 −0 arch/metag/include/uapi/asm/resource.h
  97. +31 −0 arch/metag/include/uapi/asm/sigcontext.h
  98. +8 −0 arch/metag/include/uapi/asm/siginfo.h
  99. +26 −0 arch/metag/include/uapi/asm/swab.h
  100. +21 −0 arch/metag/include/uapi/asm/unistd.h
  101. +1 −0 arch/metag/kernel/.gitignore
  102. +39 −0 arch/metag/kernel/Makefile
  103. +14 −0 arch/metag/kernel/asm-offsets.c
  104. +124 −0 arch/metag/kernel/cachepart.c
  105. +53 −0 arch/metag/kernel/clock.c
  106. +117 −0 arch/metag/kernel/core_reg.c
  107. +23 −0 arch/metag/kernel/da.c
  108. +114 −0 arch/metag/kernel/devtree.c
  109. +507 −0 arch/metag/kernel/dma.c
  110. +126 −0 arch/metag/kernel/ftrace.c
  111. +76 −0 arch/metag/kernel/ftrace_stub.S
  112. +57 −0 arch/metag/kernel/head.S
  113. +323 −0 arch/metag/kernel/irq.c
  114. +101 −0 arch/metag/kernel/kick.c
  115. +20 −0 arch/metag/kernel/machines.c
  116. +49 −0 arch/metag/kernel/metag_ksyms.c
  117. +284 −0 arch/metag/kernel/module.c
  118. +3 −0 arch/metag/kernel/perf/Makefile
  119. +861 −0 arch/metag/kernel/perf/perf_event.c
  120. +106 −0 arch/metag/kernel/perf/perf_event.h
  121. +96 −0 arch/metag/kernel/perf_callchain.c
  122. +461 −0 arch/metag/kernel/process.c
  123. +380 −0 arch/metag/kernel/ptrace.c
  124. +631 −0 arch/metag/kernel/setup.c
  125. +344 −0 arch/metag/kernel/signal.c
  126. +575 −0 arch/metag/kernel/smp.c
  127. +187 −0 arch/metag/kernel/stacktrace.c
  128. +180 −0 arch/metag/kernel/sys_metag.c
  129. +22 −0 arch/metag/kernel/tbiunexp.S
  130. +151 −0 arch/metag/kernel/tcm.c
  131. +15 −0 arch/metag/kernel/time.c
  132. +77 −0 arch/metag/kernel/topology.c
  133. +995 −0 arch/metag/kernel/traps.c
  134. +97 −0 arch/metag/kernel/user_gateway.S
  135. +71 −0 arch/metag/kernel/vmlinux.lds.S
  136. +22 −0 arch/metag/lib/Makefile
  137. +33 −0 arch/metag/lib/ashldi3.S
  138. +33 −0 arch/metag/lib/ashrdi3.S
  139. +168 −0 arch/metag/lib/checksum.c
  140. +17 −0 arch/metag/lib/clear_page.S
  141. +32 −0 arch/metag/lib/cmpdi2.S
  142. +20 −0 arch/metag/lib/copy_page.S
  143. +56 −0 arch/metag/lib/delay.c
  144. +108 −0 arch/metag/lib/div64.S
  145. +100 −0 arch/metag/lib/divsi3.S
  146. +32 −0 arch/metag/lib/ip_fast_csum.S
  147. +33 −0 arch/metag/lib/lshrdi3.S
  148. +185 −0 arch/metag/lib/memcpy.S
  149. +345 −0 arch/metag/lib/memmove.S
  150. +86 −0 arch/metag/lib/memset.S
  151. +38 −0 arch/metag/lib/modsi3.S
  152. +44 −0 arch/metag/lib/muldi3.S
  153. +27 −0 arch/metag/lib/ucmpdi2.S
  154. +1,354 −0 arch/metag/lib/usercopy.c
  155. +153 −0 arch/metag/mm/Kconfig
  156. +19 −0 arch/metag/mm/Makefile
  157. +521 −0 arch/metag/mm/cache.c
  158. +15 −0 arch/metag/mm/extable.c
  159. +239 −0 arch/metag/mm/fault.c
  160. +133 −0 arch/metag/mm/highmem.c
  161. +259 −0 arch/metag/mm/hugetlbpage.c
  162. +451 −0 arch/metag/mm/init.c
  163. +89 −0 arch/metag/mm/ioremap.c
  164. +192 −0 arch/metag/mm/l2cache.c
  165. +68 −0 arch/metag/mm/maccess.c
  166. +157 −0 arch/metag/mm/mmu-meta1.c
  167. +207 −0 arch/metag/mm/mmu-meta2.c
  168. +81 −0 arch/metag/mm/numa.c
  169. +21 −0 arch/metag/tbx/Makefile
  170. +136 −0 arch/metag/tbx/tbicore.S
  171. +366 −0 arch/metag/tbx/tbictx.S
  172. +190 −0 arch/metag/tbx/tbictxfpu.S
  173. +175 −0 arch/metag/tbx/tbidefr.S
  174. +161 −0 arch/metag/tbx/tbidspram.S
  175. +48 −0 arch/metag/tbx/tbilogf.S
  176. +451 −0 arch/metag/tbx/tbipcx.S
  177. +87 −0 arch/metag/tbx/tbiroot.S
  178. +237 −0 arch/metag/tbx/tbisoft.S
  179. +114 −0 arch/metag/tbx/tbistring.c
  180. +207 −0 arch/metag/tbx/tbitimer.S
  181. +5 −0 drivers/clocksource/Kconfig
  182. +1 −0 drivers/clocksource/Makefile
  183. +198 −0 drivers/clocksource/metag_generic.c
  184. +2 −0 drivers/irqchip/Makefile
  185. +868 −0 drivers/irqchip/irq-metag-ext.c
  186. +343 −0 drivers/irqchip/irq-metag.c
  187. +4 −0 fs/binfmt_elf.c
  188. +2 −0 include/asm-generic/io.h
  189. +8 −1 include/asm-generic/unistd.h
  190. +21 −0 include/clocksource/metag_generic.h
  191. +33 −0 include/linux/irqchip/metag-ext.h
  192. +24 −0 include/linux/irqchip/metag.h
  193. +2 −0 include/linux/mm.h
  194. +2 −0 include/uapi/linux/elf.h
  195. +4 −2 kernel/trace/ring_buffer.c
  196. +2 −2 lib/Kconfig.debug
  197. +6 −2 scripts/checkstack.pl
  198. +2 −1 scripts/genksyms/genksyms.c
  199. +13 −0 scripts/recordmcount.c
  200. +6 −0 tools/perf/perf.h
View
@@ -299,6 +299,8 @@ memory-hotplug.txt
- Hotpluggable memory support, how to use and current status.
memory.txt
- info on typical Linux memory problems.
+metag/
+ - directory with info about Linux on Meta architecture.
mips/
- directory with info about Linux on MIPS architecture.
misc-devices/
@@ -0,0 +1,82 @@
+* Meta External Trigger Controller Binding
+
+This binding specifies what properties must be available in the device tree
+representation of a Meta external trigger controller.
+
+Required properties:
+
+ - compatible: Specifies the compatibility list for the interrupt controller.
+ The type shall be <string> and the value shall include "img,meta-intc".
+
+ - num-banks: Specifies the number of interrupt banks (each of which can
+ handle 32 interrupt sources).
+
+ - interrupt-controller: The presence of this property identifies the node
+ as an interupt controller. No property value shall be defined.
+
+ - #interrupt-cells: Specifies the number of cells needed to encode an
+ interrupt source. The type shall be a <u32> and the value shall be 2.
+
+ - #address-cells: Specifies the number of cells needed to encode an
+ address. The type shall be <u32> and the value shall be 0. As such,
+ 'interrupt-map' nodes do not have to specify a parent unit address.
+
+Optional properties:
+
+ - no-mask: The controller doesn't have any mask registers.
+
+* Interrupt Specifier Definition
+
+ Interrupt specifiers consists of 2 cells encoded as follows:
+
+ - <1st-cell>: The interrupt-number that identifies the interrupt source.
+
+ - <2nd-cell>: The Linux interrupt flags containing level-sense information,
+ encoded as follows:
+ 1 = edge triggered
+ 4 = level-sensitive
+
+* Examples
+
+Example 1:
+
+ /*
+ * Meta external trigger block
+ */
+ intc: intc {
+ // This is an interrupt controller node.
+ interrupt-controller;
+
+ // No address cells so that 'interrupt-map' nodes which
+ // reference this interrupt controller node do not need a parent
+ // address specifier.
+ #address-cells = <0>;
+
+ // Two cells to encode interrupt sources.
+ #interrupt-cells = <2>;
+
+ // Number of interrupt banks
+ num-banks = <2>;
+
+ // No HWMASKEXT is available (specify on Chorus2 and Comet ES1)
+ no-mask;
+
+ // Compatible with Meta hardware trigger block.
+ compatible = "img,meta-intc";
+ };
+
+Example 2:
+
+ /*
+ * An interrupt generating device that is wired to a Meta external
+ * trigger block.
+ */
+ uart1: uart@0x02004c00 {
+ // Interrupt source '5' that is level-sensitive.
+ // Note that there are only two cells as specified in the
+ // interrupt parent's '#interrupt-cells' property.
+ interrupts = <5 4 /* level */>;
+
+ // The interrupt controller that this device is wired to.
+ interrupt-parent = <&intc>;
+ };
@@ -978,6 +978,10 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
If specified, z/VM IUCV HVC accepts connections
from listed z/VM user IDs only.
+ hwthread_map= [METAG] Comma-separated list of Linux cpu id to
+ hardware thread id mappings.
+ Format: <cpu>:<hwthread>
+
keep_bootcon [KNL]
Do not unregister boot console at start. This is only
useful for debugging when something happens in the window
@@ -0,0 +1,4 @@
+00-INDEX
+ - this file
+kernel-ABI.txt
+ - Documents metag ABI details
@@ -0,0 +1,256 @@
+ ==========================
+ KERNEL ABIS FOR METAG ARCH
+ ==========================
+
+This document describes the Linux ABIs for the metag architecture, and has the
+following sections:
+
+ (*) Outline of registers
+ (*) Userland registers
+ (*) Kernel registers
+ (*) System call ABI
+ (*) Calling conventions
+
+
+====================
+OUTLINE OF REGISTERS
+====================
+
+The main Meta core registers are arranged in units:
+
+ UNIT Type DESCRIPTION GP EXT PRIV GLOBAL
+ ======= ======= =============== ======= ======= ======= =======
+ CT Special Control unit
+ D0 General Data unit 0 0-7 8-15 16-31 16-31
+ D1 General Data unit 1 0-7 8-15 16-31 16-31
+ A0 General Address unit 0 0-3 4-7 8-15 8-15
+ A1 General Address unit 1 0-3 4-7 8-15 8-15
+ PC Special PC unit 0 1
+ PORT Special Ports
+ TR Special Trigger unit 0-7
+ TT Special Trace unit 0-5
+ FX General FP unit 0-15
+
+GP registers form part of the main context.
+
+Extended context registers (EXT) may not be present on all hardware threads and
+can be context switched if support is enabled and the appropriate bits are set
+in e.g. the D0.8 register to indicate what extended state to preserve.
+
+Global registers are shared between threads and are privilege protected.
+
+See arch/metag/include/asm/metag_regs.h for definitions relating to core
+registers and the fields and bits they contain. See the TRMs for further details
+about special registers.
+
+Several special registers are preserved in the main context, these are the
+interesting ones:
+
+ REG (ALIAS) PURPOSE
+ ======================= ===============================================
+ CT.1 (TXMODE) Processor mode bits (particularly for DSP)
+ CT.2 (TXSTATUS) Condition flags and LSM_STEP (MGET/MSET step)
+ CT.3 (TXRPT) Branch repeat counter
+ PC.0 (PC) Program counter
+
+Some of the general registers have special purposes in the ABI and therefore
+have aliases:
+
+ D0 REG (ALIAS) PURPOSE D1 REG (ALIAS) PURPOSE
+ =============== =============== =============== =======================
+ D0.0 (D0Re0) 32bit result D1.0 (D1Re0) Top half of 64bit result
+ D0.1 (D0Ar6) Argument 6 D1.1 (D1Ar5) Argument 5
+ D0.2 (D0Ar4) Argument 4 D1.2 (D1Ar3) Argument 3
+ D0.3 (D0Ar2) Argument 2 D1.3 (D1Ar1) Argument 1
+ D0.4 (D0FrT) Frame temp D1.4 (D1RtP) Return pointer
+ D0.5 Call preserved D1.5 Call preserved
+ D0.6 Call preserved D1.6 Call preserved
+ D0.7 Call preserved D1.7 Call preserved
+
+ A0 REG (ALIAS) PURPOSE A1 REG (ALIAS) PURPOSE
+ =============== =============== =============== =======================
+ A0.0 (A0StP) Stack pointer A1.0 (A1GbP) Global base pointer
+ A0.1 (A0FrP) Frame pointer A1.1 (A1LbP) Local base pointer
+ A0.2 A1.2
+ A0.3 A1.3
+
+
+==================
+USERLAND REGISTERS
+==================
+
+All the general purpose D0, D1, A0, A1 registers are preserved when entering the
+kernel (including asynchronous events such as interrupts and timer ticks) except
+the following which have special purposes in the ABI:
+
+ REGISTERS WHEN STATUS PURPOSE
+ =============== ======= =============== ===============================
+ D0.8 DSP Preserved ECH, determines what extended
+ DSP state to preserve.
+ A0.0 (A0StP) ALWAYS Preserved Stack >= A0StP may be clobbered
+ at any time by the creation of a
+ signal frame.
+ A1.0 (A1GbP) SMP Clobbered Used as temporary for loading
+ kernel stack pointer and saving
+ core context.
+ A0.15 !SMP Protected Stores kernel stack pointer.
+ A1.15 ALWAYS Protected Stores kernel base pointer.
+
+On UP A0.15 is used to store the kernel stack pointer for storing the userland
+context. A0.15 is global between hardware threads though which means it cannot
+be used on SMP for this purpose. Since no protected local registers are
+available A1GbP is reserved for use as a temporary to allow a percpu stack
+pointer to be loaded for storing the rest of the context.
+
+
+================
+KERNEL REGISTERS
+================
+
+When in the kernel the following registers have special purposes in the ABI:
+
+ REGISTERS WHEN STATUS PURPOSE
+ =============== ======= =============== ===============================
+ A0.0 (A0StP) ALWAYS Preserved Stack >= A0StP may be clobbered
+ at any time by the creation of
+ an irq signal frame.
+ A1.0 (A1GbP) ALWAYS Preserved Reserved (kernel base pointer).
+
+
+===============
+SYSTEM CALL ABI
+===============
+
+When a system call is made, the following registers are effective:
+
+ REGISTERS CALL RETURN
+ =============== ======================= ===============================
+ D0.0 (D0Re0) Return value (or -errno)
+ D1.0 (D1Re0) System call number Clobbered
+ D0.1 (D0Ar6) Syscall arg #6 Preserved
+ D1.1 (D1Ar5) Syscall arg #5 Preserved
+ D0.2 (D0Ar4) Syscall arg #4 Preserved
+ D1.2 (D1Ar3) Syscall arg #3 Preserved
+ D0.3 (D0Ar2) Syscall arg #2 Preserved
+ D1.3 (D1Ar1) Syscall arg #1 Preserved
+
+Due to the limited number of argument registers and some system calls with badly
+aligned 64-bit arguments, 64-bit values are always packed in consecutive
+arguments, even if this is contrary to the normal calling conventions (where the
+two halves would go in a matching pair of data registers).
+
+For example fadvise64_64 usually has the signature:
+
+ long sys_fadvise64_64(i32 fd, i64 offs, i64 len, i32 advice);
+
+But for metag fadvise64_64 is wrapped so that the 64-bit arguments are packed:
+
+ long sys_fadvise64_64_metag(i32 fd, i32 offs_lo,
+ i32 offs_hi, i32 len_lo,
+ i32 len_hi, i32 advice)
+
+So the arguments are packed in the registers like this:
+
+ D0 REG (ALIAS) VALUE D1 REG (ALIAS) VALUE
+ =============== =============== =============== =======================
+ D0.1 (D0Ar6) advice D1.1 (D1Ar5) hi(len)
+ D0.2 (D0Ar4) lo(len) D1.2 (D1Ar3) hi(offs)
+ D0.3 (D0Ar2) lo(offs) D1.3 (D1Ar1) fd
+
+
+===================
+CALLING CONVENTIONS
+===================
+
+These calling conventions apply to both user and kernel code. The stack grows
+from low addresses to high addresses in the metag ABI. The stack pointer (A0StP)
+should always point to the next free address on the stack and should at all
+times be 64-bit aligned. The following registers are effective at the point of a
+call:
+
+ REGISTERS CALL RETURN
+ =============== ======================= ===============================
+ D0.0 (D0Re0) 32bit return value
+ D1.0 (D1Re0) Upper half of 64bit return value
+ D0.1 (D0Ar6) 32bit argument #6 Clobbered
+ D1.1 (D1Ar5) 32bit argument #5 Clobbered
+ D0.2 (D0Ar4) 32bit argument #4 Clobbered
+ D1.2 (D1Ar3) 32bit argument #3 Clobbered
+ D0.3 (D0Ar2) 32bit argument #2 Clobbered
+ D1.3 (D1Ar1) 32bit argument #1 Clobbered
+ D0.4 (D0FrT) Clobbered
+ D1.4 (D1RtP) Return pointer Clobbered
+ D{0-1}.{5-7} Preserved
+ A0.0 (A0StP) Stack pointer Preserved
+ A1.0 (A0GbP) Preserved
+ A0.1 (A0FrP) Frame pointer Preserved
+ A1.1 (A0LbP) Preserved
+ A{0-1},{2-3} Clobbered
+
+64-bit arguments are placed in matching pairs of registers (i.e. the same
+register number in both D0 and D1 units), with the least significant half in D0
+and the most significant half in D1, leaving a gap where necessary. Futher
+arguments are stored on the stack in reverse order (earlier arguments at higher
+addresses):
+
+ ADDRESS 0 1 2 3 4 5 6 7
+ =============== ===== ===== ===== ===== ===== ===== ===== =====
+ A0StP -->
+ A0StP-0x08 32bit argument #8 32bit argument #7
+ A0StP-0x10 32bit argument #10 32bit argument #9
+
+Function prologues tend to look a bit like this:
+
+ /* If frame pointer in use, move it to frame temp register so it can be
+ easily pushed onto stack */
+ MOV D0FrT,A0FrP
+
+ /* If frame pointer in use, set it to stack pointer */
+ ADD A0FrP,A0StP,#0
+
+ /* Preserve D0FrT, D1RtP, D{0-1}.{5-7} on stack, incrementing A0StP */
+ MSETL [A0StP++],D0FrT,D0.5,D0.6,D0.7
+
+ /* Allocate some stack space for local variables */
+ ADD A0StP,A0StP,#0x10
+
+At this point the stack would look like this:
+
+ ADDRESS 0 1 2 3 4 5 6 7
+ =============== ===== ===== ===== ===== ===== ===== ===== =====
+ A0StP -->
+ A0StP-0x08
+ A0StP-0x10
+ A0StP-0x18 Old D0.7 Old D1.7
+ A0StP-0x20 Old D0.6 Old D1.6
+ A0StP-0x28 Old D0.5 Old D1.5
+ A0FrP --> Old A0FrP (frame ptr) Old D1RtP (return ptr)
+ A0FrP-0x08 32bit argument #8 32bit argument #7
+ A0FrP-0x10 32bit argument #10 32bit argument #9
+
+Function epilogues tend to differ depending on the use of a frame pointer. An
+example of a frame pointer epilogue:
+
+ /* Restore D0FrT, D1RtP, D{0-1}.{5-7} from stack, incrementing A0FrP */
+ MGETL D0FrT,D0.5,D0.6,D0.7,[A0FrP++]
+ /* Restore stack pointer to where frame pointer was before increment */
+ SUB A0StP,A0FrP,#0x20
+ /* Restore frame pointer from frame temp */
+ MOV A0FrP,D0FrT
+ /* Return to caller via restored return pointer */
+ MOV PC,D1RtP
+
+If the function hasn't touched the frame pointer, MGETL cannot be safely used
+with A0StP as it always increments and that would expose the stack to clobbering
+by interrupts (kernel) or signals (user). Therefore it's common to see the MGETL
+split into separate GETL instructions:
+
+ /* Restore D0FrT, D1RtP, D{0-1}.{5-7} from stack */
+ GETL D0FrT,D1RtP,[A0StP+#-0x30]
+ GETL D0.5,D1.5,[A0StP+#-0x28]
+ GETL D0.6,D1.6,[A0StP+#-0x20]
+ GETL D0.7,D1.7,[A0StP+#-0x18]
+ /* Restore stack pointer */
+ SUB A0StP,A0StP,#0x30
+ /* Return to caller via restored return pointer */
+ MOV PC,D1RtP
View
@@ -5204,6 +5204,18 @@ F: drivers/mtd/
F: include/linux/mtd/
F: include/uapi/mtd/
+METAG ARCHITECTURE
+M: James Hogan <james.hogan@imgtec.com>
+S: Supported
+F: arch/metag/
+F: Documentation/metag/
+F: Documentation/devicetree/bindings/metag/
+F: drivers/clocksource/metag_generic.c
+F: drivers/irqchip/irq-metag.c
+F: drivers/irqchip/irq-metag-ext.c
+F: drivers/tty/metag_da.c
+F: fs/imgdafs/
+
MICROBLAZE ARCHITECTURE
M: Michal Simek <monstr@monstr.eu>
L: microblaze-uclinux@itee.uq.edu.au (moderated for non-subscribers)
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