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Merge branch 'for-linus' of git://git.infradead.org/users/vkoul/slave…
…-dma Pull dmaengine updates from Vinod Koul: "This update brings: - the big cleanup up by Maxime for device control and slave capabilities. This makes the API much cleaner. - new IMG MDC driver by Andrew - new Renesas R-Car Gen2 DMA Controller driver by Laurent along with bunch of fixes on rcar drivers - odd fixes and updates spread over driver" * 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma: (130 commits) dmaengine: pl330: add DMA_PAUSE feature dmaengine: pl330: improve pl330_tx_status() function dmaengine: rcar-dmac: Disable channel 0 when using IOMMU dmaengine: rcar-dmac: Work around descriptor mode IOMMU errata dmaengine: rcar-dmac: Allocate hardware descriptors with DMAC device dmaengine: rcar-dmac: Fix oops due to unintialized list in error ISR dmaengine: rcar-dmac: Fix spinlock issues in interrupt dmaenegine: edma: fix sparse warnings dmaengine: rcar-dmac: Fix uninitialized variable usage dmaengine: shdmac: extend PM methods dmaengine: shdmac: use SET_RUNTIME_PM_OPS() dmaengine: pl330: fix bug that cause start the same descs in cyclic dmaengine: at_xdmac: allow muliple dwidths when doing slave transfers dmaengine: at_xdmac: simplify channel configuration stuff dmaengine: at_xdmac: introduce save_cc field dmaengine: at_xdmac: wait for in-progress transaction to complete after pausing a channel ioat: fail self-test if wait_for_completion times out dmaengine: dw: define DW_DMA_MAX_NR_MASTERS dmaengine: dw: amend description of dma_dev field dmatest: move src_off, dst_off, len inside loop ...
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* IMG Multi-threaded DMA Controller (MDC) | ||
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Required properties: | ||
- compatible: Must be "img,pistachio-mdc-dma". | ||
- reg: Must contain the base address and length of the MDC registers. | ||
- interrupts: Must contain all the per-channel DMA interrupts. | ||
- clocks: Must contain an entry for each entry in clock-names. | ||
See ../clock/clock-bindings.txt for details. | ||
- clock-names: Must include the following entries: | ||
- sys: MDC system interface clock. | ||
- img,cr-periph: Must contain a phandle to the peripheral control syscon | ||
node which contains the DMA request to channel mapping registers. | ||
- img,max-burst-multiplier: Must be the maximum supported burst size multiplier. | ||
The maximum burst size is this value multiplied by the hardware-reported bus | ||
width. | ||
- #dma-cells: Must be 3: | ||
- The first cell is the peripheral's DMA request line. | ||
- The second cell is a bitmap specifying to which channels the DMA request | ||
line may be mapped (i.e. bit N set indicates channel N is usable). | ||
- The third cell is the thread ID to be used by the channel. | ||
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Optional properties: | ||
- dma-channels: Number of supported DMA channels, up to 32. If not specified | ||
the number reported by the hardware is used. | ||
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Example: | ||
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mdc: dma-controller@18143000 { | ||
compatible = "img,pistachio-mdc-dma"; | ||
reg = <0x18143000 0x1000>; | ||
interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SHARED 29 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SHARED 30 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SHARED 31 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SHARED 32 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SHARED 33 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SHARED 34 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SHARED 35 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SHARED 36 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SHARED 38 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&system_clk>; | ||
clock-names = "sys"; | ||
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img,max-burst-multiplier = <16>; | ||
img,cr-periph = <&cr_periph>; | ||
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#dma-cells = <3>; | ||
}; | ||
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spi@18100f00 { | ||
... | ||
dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>; | ||
dma-names = "tx", "rx"; | ||
... | ||
}; |
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