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Commits on Feb 21, 2015
  1. Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.tu…

    authored
    …rquette/linux
    
    Pull clock framework updates from Mike Turquette:
     "The clock framework changes contain the usual driver additions,
      enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
      devices.
    
      Additionally the framework core underwent a bit of surgery with two
      major changes:
    
       - The boundary between the clock core and clock providers (e.g clock
         drivers) is now more well defined with dedicated provider helper
         functions.  struct clk no longer maps 1:1 with the hardware clock
         but is a true per-user cookie which helps us tracker users of
         hardware clocks and debug bad behavior.
    
       - The addition of rate constraints for clocks.  Rate ranges are now
         supported which are analogous to the voltage ranges in the
         regulator framework.
    
      Unfortunately these changes to the core created some breakeage.  We
      think we fixed it all up but for this reason there are lots of last
      minute commits trying to undo the damage"
    
    * tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits)
      clk: Only recalculate the rate if needed
      Revert "clk: mxs: Fix invalid 32-bit access to frac registers"
      clk: qoriq: Add support for the platform PLL
      powerpc/corenet: Enable CLK_QORIQ
      clk: Replace explicit clk assignment with __clk_hw_set_clk
      clk: Add __clk_hw_set_clk helper function
      clk: Don't dereference parent clock if is NULL
      MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr
      clkdev: Always allocate a struct clk and call __clk_get() w/ CCF
      clk: shmobile: div6: Avoid division by zero in .round_rate()
      clk: mxs: Fix invalid 32-bit access to frac registers
      clk: omap: compile legacy omap3 clocks conditionally
      clkdev: Export clk_register_clkdev
      clk: Add rate constraints to clocks
      clk: remove clk-private.h
      pci: xgene: do not use clk-private.h
      arm: omap2+ remove dead clock code
      clk: Make clk API return per-user struct clk instances
      clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
      clk: tegra: Add support for the Tegra132 CAR IP block
      ...
Commits on Feb 20, 2015
  1. Tomeu Vizoso Mike Turquette

    clk: Only recalculate the rate if needed

    tomeuv authored mturquette committed
    We don't really need to recalculate the effective rate of a clock when a
    per-user clock is removed, if the constraints of the later aren't
    limiting the requested rate.
    
    This was causing problems with clocks that never had a rate set before,
    as rate_req would be zero. Though this could be considered a bug in the
    implementation of those clocks, this should be checked somewhere else.
    
    Fixes: 1c8e600 ("clk: Add rate constraints to clocks")
    Cc: Thierry Reding <thierry.reding@gmail.com>
    Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
    Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
    Signed-off-by: Michael Turquette <mturquette@linaro.org>
Commits on Feb 18, 2015
  1. Stefan Wahren Mike Turquette

    Revert "clk: mxs: Fix invalid 32-bit access to frac registers"

    lategoodbye authored mturquette committed
    Revert commit 039e597 (clk: mxs: Fix invalid 32-bit access to frac
    registers), because it leads to a faulty spi communication on mx28evk.
    
    Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
    Reported-by: Fabio Estevam <fabio.estevam@freescale.com>
    Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
    Signed-off-by: Michael Turquette <mturquette@linaro.org>
  2. Mike Turquette

    clk: qoriq: Add support for the platform PLL

    Emil Medve authored mturquette committed
    Change-Id: Iac11ed95f274485a86d2c11f32a3dc502bcd020f
    Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
    Acked-by: Tang Yuantian <Yuantian.Tang@freescale.com>
    Signed-off-by: Michael Turquette <mturquette@linaro.org>
  3. Javier Martinez Canillas Mike Turquette

    clk: Replace explicit clk assignment with __clk_hw_set_clk

    martinezjavier authored mturquette committed
    The change in the clk API to return a per-user clock instance, moved
    the clock state to struct clk_core so now the struct clk_hw .core field
    is used instead of .clk for most operations.
    
    So for hardware clocks that needs to share the same clock state, both
    the .core and .clk pointers have to be assigned but currently only the
    .clk is set. This leads to NULL pointer dereference when the operations
    try to access the hw clock .core. For example, the composite clock rate
    and mux components didn't have a .core set which leads to this error:
    
    Unable to handle kernel NULL pointer dereference at virtual address 00000034
    pgd = c0004000
    [00000034] *pgd=00000000
    Internal error: Oops: 5 [#1] PREEMPT SMP ARM
    Modules linked in:
    CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.19.0-next-20150211-00002-g1fb7f0e1150d #423
    Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
    task: ee480000 ti: ee488000 task.ti: ee488000
    PC is at clk_mux_determine_rate_flags+0x14/0x19c
    LR is at __clk_mux_determine_rate+0x24/0x2c
    pc : [<c03a355c>]    lr : [<c03a3734>]    psr: a0000113
    sp : ee489ce8  ip : ee489d84  fp : ee489d84
    r10: 0000005c  r9 : 00000001  r8 : 016e3600
    r7 : 00000000  r6 : 00000000  r5 : ee442200  r4 : ee440c98
    r3 : ffffffff  r2 : 00000000  r1 : 016e3600  r0 : ee440c98
    Flags: NzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
    Control: 10c5387d  Table: 4000406a  DAC: 00000015
    Process swapper/0 (pid: 1, stack limit = 0xee488210)
    Stack: (0xee489ce8 to 0xee48a000)
    9ce0:                   00000000 ffffffff 60000113 ee440c98 ee442200 00000000
    9d00: 016e3600 ffffffff 00000001 0000005c ee489d84 c03a3734 ee489d80 ee489d84
    9d20: 00000000 c048b130 00000400 c03a5798 ee489d80 ee489d84 c0607f60 ffffffea
    9d40: 00000001 00000001 ee489d5c c003f844 c06e3340 ee402680 ee440d0c ed935000
    9d60: 016e3600 00000003 00000001 0000005c eded3700 c03a11a0 ee489d80 ee489d84
    9d80: 016e3600 ee402680 c05b413a eddc9900 016e3600 c03a1228 00000000 ffffffff
    9da0: ffffffff eddc9900 016e3600 c03a1c1c ffffffff 016e3600 ed8c6710 c03d6ce4
    9dc0: eded3400 00000000 00000000 c03c797c 00000001 0000005c eded3700 eded3700
    9de0: 000005e0 00000001 0000005c c03db8ac c06e7e54 c03c8f08 00000000 c06e7e64
    9e00: c06b6e74 c06e7f64 000005e0 c06e7df8 c06e5100 00000000 c06e7e6c c06e7f54
    9e20: 00000000 00000000 eebd9550 00000000 c06e7da0 c06e7e54 ee7b5010 c06e7da0
    9e40: eddc9690 c06e7db4 c06b6e74 00000097 00000000 c03d4398 00000000 ee7b5010
    9e60: eebd9550 c06e7da0 00000000 c03db824 ee7b5010 fffffffe c06e7db4 c0299c7c
    9e80: ee7b5010 c072a05c 00000000 c0298858 ee7b5010 c06e7db4 ee7b5044 00000000
    9ea0: eddc9580 c0298a04 c06e7db4 00000000 c0298978 c02971d4 ee405c78 ee732b40
    9ec0: c06e7db4 eded3800 c06d6738 c0298044 c0608300 c06e7db4 00000000 c06e7db4
    9ee0: 00000000 c06beb58 c06beb58 c0299024 00000000 c068dd00 00000000 c0008944
    9f00: 00000038 c049013c ee462200 c0711920 ee480000 60000113 c06c2cb0 00000000
    9f20: 00000000 c06c2cb0 60000113 00000000 ef7fcafc 00000000 c0640194 c00389ec
    9f40: c05ec3a8 c063f824 00000006 00000006 c06c2c50 c0696444 00000006 c0696424
    9f60: c06ee1c0 c066b588 c06b6e74 00000097 00000000 c066bd44 00000006 00000006
    9f80: c066b588 c003d684 00000000 c0481938 00000000 00000000 00000000 00000000
    9fa0: 00000000 c0481940 00000000 c000e680 00000000 00000000 00000000 00000000
    9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
    [<c03a355c>] (clk_mux_determine_rate_flags) from [<c03a3734>] (__clk_mux_determine_rate+0x24/0x2c)
    [<c03a3734>] (__clk_mux_determine_rate) from [<c03a5798>] (clk_composite_determine_rate+0xbc/0x238)
    [<c03a5798>] (clk_composite_determine_rate) from [<c03a11a0>] (clk_core_round_rate_nolock+0x5c/0x9c)
    [<c03a11a0>] (clk_core_round_rate_nolock) from [<c03a1228>] (__clk_round_rate+0x38/0x40)
    [<c03a1228>] (__clk_round_rate) from [<c03a1c1c>] (clk_round_rate+0x20/0x38)
    [<c03a1c1c>] (clk_round_rate) from [<c03d6ce4>] (max98090_dai_set_sysclk+0x34/0x118)
    [<c03d6ce4>] (max98090_dai_set_sysclk) from [<c03c797c>] (snd_soc_dai_set_sysclk+0x38/0x80)
    [<c03c797c>] (snd_soc_dai_set_sysclk) from [<c03db8ac>] (snow_late_probe+0x24/0x48)
    [<c03db8ac>] (snow_late_probe) from [<c03c8f08>] (snd_soc_register_card+0xf04/0x1070)
    [<c03c8f08>] (snd_soc_register_card) from [<c03d4398>] (devm_snd_soc_register_card+0x30/0x64)
    [<c03d4398>] (devm_snd_soc_register_card) from [<c03db824>] (snow_probe+0x68/0xcc)
    [<c03db824>] (snow_probe) from [<c0299c7c>] (platform_drv_probe+0x48/0x98)
    [<c0299c7c>] (platform_drv_probe) from [<c0298858>] (driver_probe_device+0x114/0x234)
    [<c0298858>] (driver_probe_device) from [<c0298a04>] (__driver_attach+0x8c/0x90)
    [<c0298a04>] (__driver_attach) from [<c02971d4>] (bus_for_each_dev+0x54/0x88)
    [<c02971d4>] (bus_for_each_dev) from [<c0298044>] (bus_add_driver+0xd8/0x1cc)
    [<c0298044>] (bus_add_driver) from [<c0299024>] (driver_register+0x78/0xf4)
    [<c0299024>] (driver_register) from [<c0008944>] (do_one_initcall+0x80/0x1d0)
    [<c0008944>] (do_one_initcall) from [<c066bd44>] (kernel_init_freeable+0x10c/0x1d8)
    [<c066bd44>] (kernel_init_freeable) from [<c0481940>] (kernel_init+0x8/0xe4)
    [<c0481940>] (kernel_init) from [<c000e680>] (ret_from_fork+0x14/0x34)
    Code: e24dd00c e5907000 e1a08001 e88d000c (e5970034)
    
    The changes were made using the following cocinelle semantic patch:
    
    @i@
    @@
    
    @depends on i@
    identifier dst;
    @@
    
    - dst->clk = hw->clk;
    + __clk_hw_set_clk(dst, hw);
    
    @depends on i@
    identifier dst;
    @@
    
    - dst->hw.clk = hw->clk;
    + __clk_hw_set_clk(&dst->hw, hw);
    
    Fixes: 035a61c ("clk: Make clk API return per-user struct clk instances")
    Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
    Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
    Signed-off-by: Michael Turquette <mturquette@linaro.org>
  4. Javier Martinez Canillas Mike Turquette

    clk: Don't dereference parent clock if is NULL

    martinezjavier authored mturquette committed
    The clock passed as an argument to clk_mux_determine_rate_flags()
    has the CLK_SET_RATE_PARENT flag set but it has no parent, then a
    NULL pointer will tried to be dereferenced.
    
    This shouldn't happen since setting that flag for a clock with no
    parent is a bug but the core should be robust to handle that case.
    
    Fixes: 035a61c ("clk: Make clk API return per-user struct clk instances")
    Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
    Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
    Signed-off-by: Michael Turquette <mturquette@linaro.org>
Commits on Feb 17, 2015
  1. Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/k…

    authored
    …ernel/git/arm/arm-soc
    
    Pull ARM SoC driver updates from Olof Johansson:
     "These are changes for drivers that are intimately tied to some SoC and
      for some reason could not get merged through the respective subsystem
      maintainer tree.
    
      This time around, much of this is for at91, with the bulk of it being
      syscon and udc drivers.
    
      Also, there's:
       - coupled cpuidle support for Samsung Exynos4210
       - Renesas 73A0 common-clk work
       - of/platform changes to tear down DMA mappings on device destruction
       - a few updates to the TI Keystone knav code"
    
    * tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (26 commits)
      cpuidle: exynos: add coupled cpuidle support for exynos4210
      ARM: EXYNOS: apply S5P_CENTRAL_SEQ_OPTION fix only when necessary
      soc: ti: knav_qmss_queue: change knav_range_setup_acc_irq to static
      soc: ti: knav_qmss_queue: makefile tweak to build as dynamic module
      pcmcia: at91_cf: depend on !ARCH_MULTIPLATFORM
      soc: ti: knav_qmss_queue: export API calls for use by user driver
      of/platform: teardown DMA mappings on device destruction
      usb: gadget: at91_udc: Allocate udc instance
      usb: gadget: at91_udc: Update DT binding documentation
      usb: gadget: at91_udc: Rework for multi-platform kernel support
      usb: gadget: at91_udc: Simplify probe and remove functions
      usb: gadget: at91_udc: Remove non-DT handling code
      usb: gadget: at91_udc: Document DT clocks and clock-names property
      usb: gadget: at91_udc: Drop uclk clock
      usb: gadget: at91_udc: Fix clock names
      mfd: syscon: Add Atmel SMC binding doc
      mfd: syscon: Add atmel-smc registers definition
      mfd: syscon: Add Atmel Matrix bus DT binding documentation
      mfd: syscon: Add atmel-matrix registers definition
      clk: shmobile: fix sparse NULL pointer warning
      ...
  2. Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel…

    authored
    …/git/arm/arm-soc
    
    Pull ARM SoC DT updates from Olof Johansson:
     "DT changes continue to be the bulk of our merge window contents.
    
      We continue to have a large set of changes across the board as new
      platforms and drivers are added.
    
      Some of the new platforms are:
       - Alphascale ASM9260
       - Marvell Armada 388
       - CSR Atlas7
       - TI Davinci DM816x
       - Hisilicon HiP01
       - ST STiH418
    
      There have also been some sweeping changes, including relicensing of
      DTS contents from GPL to GPLv2+/X11 so that the same files can be
      reused in other non-GPL projects more easily.  There's also been
      changes to the DT Makefile to make it a little less conflict-ridden
      and churny down the road"
    
    * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (330 commits)
      ARM: dts: Add PPMU node for exynos4412-trats2
      ARM: dts: Add PPMU node for exynos3250-monk and exynos3250-rinato
      ARM: dts: Add PPMU dt node for exynos4 and exynos4210
      ARM: dts: Add PPMU dt node for exynos3250
      ARM: dts: add mipi dsi device node for exynos4415
      ARM: dts: add fimd device node for exynos4415
      ARM: dts: Add syscon phandle to the video-phy node for Exynos4
      ARM: dts: Add sound nodes for exynos4412-trats2
      ARM: dts: Fix CLK_MOUT_CAMn parent clocks assignment for exynos4412-trats2
      ARM: dts: Fix CLK_UART_ISP_SCLK clock assignment in exynos4x12.dtsi
      ARM: dts: Add max77693 charger node for exynos4412-trats2
      ARM: dts: Switch max77686 regulators to GPIO control for exynos4412-trats2
      ARM: dts: Add suspend configuration for max77686 regulators for exynos4412-trats2
      ARM: dts: Add Maxim 77693 fuel gauge node for exynos4412-trats2
      ARM: dts: am57xx-beagle-x15: Fix USB2 mode
      ARM: dts: am57xx-beagle-x15: Add extcon nodes for USB
      ARM: dts: dra72-evm: Add extcon nodes for USB
      ARM: dts: dra7-evm: Add extcon nodes for USB
      ARM: dts: rockchip: move the hdmi ddc-i2c-bus property to the actual boards
      ARM: dts: rockchip: enable vops and hdmi output on rk3288-firefly and -evb
      ...
  3. Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kerne…

    authored
    …l/git/arm/arm-soc
    
    Pull ARM SoC platform changes from Olof Johansson:
     "New and updated SoC support.  Also included are some cleanups where
      the platform maintainers hadn't separated cleanups from new developent
      in separate branches.
    
      Some of the larger things worth pointing out:
    
       - A large set of changes from Alexandre Belloni and Nicolas Ferre
         preparing at91 platforms for multiplatform and cleaning up quite a
         bit in the process.
    
       - Removal of CSR's "Marco" SoC platform that never made it out to the
         market.  We love seeing these since it means the vendor published
         support before product was out, which is exactly what we want!
    
      New platforms this release are:
    
       - Conexant Digicolor (CX92755 SoC)
       - Hisilicon HiP01 SoC
       - CSR/sirf Atlas7 SoC
       - ST STiH418 SoC
       - Common code changes for Nvidia Tegra132 (64-bit SoC)
    
      We're seeing more and more platforms having a harder time labelling
      changes as cleanups vs new development -- which is a good sign that
      we've come quite far on the cleanup effort.  So over time we might
      start combining the cleanup and new-development branches more"
    
    * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (124 commits)
      ARM: at91/trivial: unify functions and machine names
      ARM: at91: remove at91_dt_initialize and machine init_early()
      ARM: at91: change board files into SoC files
      ARM: at91: remove at91_boot_soc
      ARM: at91: move alternative initial mapping to board-dt-sama5.c
      ARM: at91: merge all SOC_AT91SAM9xxx
      ARM: at91: at91rm9200: set idle and restart from rm9200_dt_device_init()
      ARM: digicolor: select syscon and timer
      ARM: zynq: Simplify SLCR initialization
      ARM: zynq: PM: Fixed simple typo.
      ARM: zynq: Setup default gpio number for Xilinx Zynq
      ARM: digicolor: add low level debug support
      ARM: initial support for Conexant Digicolor CX92755 SoC
      ARM: OMAP2+: Add dm816x hwmod support
      ARM: OMAP2+: Add clock domain support for dm816x
      ARM: OMAP2+: Add board-generic.c entry for ti81xx
      ARM: at91: pm: remove warning to remove SOC_AT91SAM9263 usage
      ARM: at91: remove unused mach/system_rev.h
      ARM: at91: stop using HAVE_AT91_DBGUx
      ARM: at91: fix ordering of SRAM and PM initialization
      ...
Commits on Feb 14, 2015
  1. clk: convert clock name allocations to kstrdup_const

    Andrzej Hajda authored committed
    Clock subsystem frequently performs duplication of strings located in
    read-only memory section.  Replacing kstrdup by kstrdup_const allows to
    avoid such operations.
    
    Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
    Cc: Marek Szyprowski <m.szyprowski@samsung.com>
    Cc: Kyungmin Park <kyungmin.park@samsung.com>
    Cc: Mike Turquette <mturquette@linaro.org>
    Cc: Alexander Viro <viro@zeniv.linux.org.uk>
    Cc: Christoph Lameter <cl@linux.com>
    Cc: Pekka Enberg <penberg@kernel.org>
    Cc: David Rientjes <rientjes@google.com>
    Cc: Joonsoo Kim <iamjoonsoo.kim@lge.com>
    Cc: Tejun Heo <tj@kernel.org>
    Cc: Greg KH <greg@kroah.com>
    Cc: Geert Uytterhoeven <geert@linux-m68k.org>
    Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
    Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Commits on Feb 11, 2015
  1. Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next

    authored
    Pull networking updates from David Miller:
    
     1) More iov_iter conversion work from Al Viro.
    
        [ The "crypto: switch af_alg_make_sg() to iov_iter" commit was
          wrong, and this pull actually adds an extra commit on top of the
          branch I'm pulling to fix that up, so that the pre-merge state is
          ok.   - Linus ]
    
     2) Various optimizations to the ipv4 forwarding information base trie
        lookup implementation.  From Alexander Duyck.
    
     3) Remove sock_iocb altogether, from CHristoph Hellwig.
    
     4) Allow congestion control algorithm selection via routing metrics.
        From Daniel Borkmann.
    
     5) Make ipv4 uncached route list per-cpu, from Eric Dumazet.
    
     6) Handle rfs hash collisions more gracefully, also from Eric Dumazet.
    
     7) Add xmit_more support to r8169, e1000, and e1000e drivers.  From
        Florian Westphal.
    
     8) Transparent Ethernet Bridging support for GRO, from Jesse Gross.
    
     9) Add BPF packet actions to packet scheduler, from Jiri Pirko.
    
    10) Add support for uniqu flow IDs to openvswitch, from Joe Stringer.
    
    11) New NetCP ethernet driver, from Muralidharan Karicheri and Wingman
        Kwok.
    
    12) More sanely handle out-of-window dupacks, which can result in
        serious ACK storms.  From Neal Cardwell.
    
    13) Various rhashtable bug fixes and enhancements, from Herbert Xu,
        Patrick McHardy, and Thomas Graf.
    
    14) Support xmit_more in be2net, from Sathya Perla.
    
    15) Group Policy extensions for vxlan, from Thomas Graf.
    
    16) Remove Checksum Offload support for vxlan, from Tom Herbert.
    
    17) Like ipv4, support lockless transmit over ipv6 UDP sockets.  From
        Vlad Yasevich.
    
    * git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1494+1 commits)
      crypto: fix af_alg_make_sg() conversion to iov_iter
      ipv4: Namespecify TCP PMTU mechanism
      i40e: Fix for stats init function call in Rx setup
      tcp: don't include Fast Open option in SYN-ACK on pure SYN-data
      openvswitch: Only set TUNNEL_VXLAN_OPT if VXLAN-GBP metadata is set
      ipv6: Make __ipv6_select_ident static
      ipv6: Fix fragment id assignment on LE arches.
      bridge: Fix inability to add non-vlan fdb entry
      net: Mellanox: Delete unnecessary checks before the function call "vunmap"
      cxgb4: Add support in cxgb4 to get expansion rom version via ethtool
      ethtool: rename reserved1 memeber in ethtool_drvinfo for expansion ROM version
      net: dsa: Remove redundant phy_attach()
      IB/mlx4: Reset flow support for IB kernel ULPs
      IB/mlx4: Always use the correct port for mirrored multicast attachments
      net/bonding: Fix potential bad memory access during bonding events
      tipc: remove tipc_snprintf
      tipc: nl compat add noop and remove legacy nl framework
      tipc: convert legacy nl stats show to nl compat
      tipc: convert legacy nl net id get to nl compat
      tipc: convert legacy nl net id set to nl compat
      ...
Commits on Feb 7, 2015
  1. Stephen Boyd Mike Turquette

    clkdev: Always allocate a struct clk and call __clk_get() w/ CCF

    bebarino authored mturquette committed
    of_clk_get_by_clkspec() returns a struct clk pointer but it
    doesn't create a new handle for the consumers when we're using
    the common clock framework. Instead it just returns whatever the
    clk provider hands out. When the consumers go to call clk_put()
    we get an Oops.
    
    Unable to handle kernel paging request at virtual address 00200200
    pgd = c0004000
    [00200200] *pgd=00000000
    Internal error: Oops: 805 [#1] PREEMPT SMP ARM
    Modules linked in:
    CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.19.0-rc1-00104-ga251361a-dirty #992
    Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
    task: ee00b000 ti: ee088000 task.ti: ee088000
    PC is at __clk_put+0x24/0xd0
    LR is at clk_prepare_lock+0xc/0xec
    pc : [<c03eef38>]    lr : [<c03ec1f4>]    psr: 20000153
    sp : ee089de8  ip : 00000000  fp : 00000000
    r10: ee02f480  r9 : 00000001  r8 : 00000000
    r7 : ee031cc0  r6 : ee089e08  r5 : 00000000  r4 : ee02f480
    r3 : 00100100  r2 : 00200200  r1 : 0000091e  r0 : 00000001
    Flags: nzCv  IRQs on  FIQs off  Mode SVC_32  ISA ARM  Segment kernel
    Control: 10c5387d  Table: 4000404a  DAC: 00000015
    Process swapper/0 (pid: 1, stack limit = 0xee088238)
    Stack: (0xee089de8 to 0xee08a000)
    9de0:                   ee7c8f14 c03f0ec8 ee089e08 00000000 c0718dc8 00000001
    9e00: 00000000 c04ee0f0 ee7e0844 00000001 00000181 c04edb58 ee2bd320 00000000
    9e20: 00000000 c011dc5c ee16a1e0 00000000 00000000 c0718dc8 ee16a1e0 ee2bd1e0
    9e40: c0641740 ee16a1e0 00000000 ee2bd320 c0718dc8 ee1d3e10 ee1d3e10 00000000
    9e60: c0769a88 00000000 c0718dc8 00000000 00000000 c02c3124 c02c310c ee1d3e10
    9e80: c07b4eec 00000000 c0769a88 c02c1d0c ee1d3e10 c0769a88 ee1d3e44 00000000
    9ea0: c07091dc c02c1eb8 00000000 c0769a88 c02c1e2c c02c0544 ee005478 ee1676c0
    9ec0: c0769a88 ee3a4e80 c0760ce8 c02c150c c0669b90 c0769a88 c0746cd8 c0769a88
    9ee0: c0746cd8 ee2bc4c0 c0778c00 c02c24e0 00000000 c0746cd8 c0746cd8 c07091f0
    9f00: 00000000 c0008944 c04f405c 00000025 ee00b000 60000153 c074ab00 00000000
    9f20: 00000000 c074ab90 60000153 00000000 ef7fca5d c050860c 000000b6 c0036b88
    9f40: c065ecc4 c06bc728 00000006 00000006 c074ab30 ef7fca40 c0739bdc 00000006
    9f60: c0718dbc c0778c00 000000b6 c0718dc8 c06ed598 c06edd64 00000006 00000006
    9f80: c06ed598 c003b438 00000000 c04e64f4 00000000 00000000 00000000 00000000
    9fa0: 00000000 c04e64fc 00000000 c000e838 00000000 00000000 00000000 00000000
    9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 c0c0c0c0 c0c0c0c0
    [<c03eef38>] (__clk_put) from [<c03f0ec8>] (of_clk_set_defaults+0xe0/0x2c0)
    [<c03f0ec8>] (of_clk_set_defaults) from [<c02c3124>] (platform_drv_probe+0x18/0xa4)
    [<c02c3124>] (platform_drv_probe) from [<c02c1d0c>] (driver_probe_device+0x10c/0x22c)
    [<c02c1d0c>] (driver_probe_device) from [<c02c1eb8>] (__driver_attach+0x8c/0x90)
    [<c02c1eb8>] (__driver_attach) from [<c02c0544>] (bus_for_each_dev+0x54/0x88)
    [<c02c0544>] (bus_for_each_dev) from [<c02c150c>] (bus_add_driver+0xd4/0x1d0)
    [<c02c150c>] (bus_add_driver) from [<c02c24e0>] (driver_register+0x78/0xf4)
    [<c02c24e0>] (driver_register) from [<c07091f0>] (fimc_md_init+0x14/0x30)
    [<c07091f0>] (fimc_md_init) from [<c0008944>] (do_one_initcall+0x80/0x1d0)
    [<c0008944>] (do_one_initcall) from [<c06edd64>] (kernel_init_freeable+0x108/0x1d4)
    [<c06edd64>] (kernel_init_freeable) from [<c04e64fc>] (kernel_init+0x8/0xec)
    [<c04e64fc>] (kernel_init) from [<c000e838>] (ret_from_fork+0x14/0x3c)
    Code: ebfff4ae e5943014 e5942018 e3530000 (e5823000)
    
    Let's create a per-user handle here so that clk_put() can
    properly unlink it and free the handle. Now that we allocate a
    clk structure here we need to free it if __clk_get() fails so
    bury the __clk_get() call in __of_clk_get_from_provider(). We
    need to handle the same problem in clk_get_sys() so export
    __clk_free_clk() to clkdev.c and do the same thing, except let's
    use a union to make this code #ifdef free.
    
    This fixes the above crash, properly calls __clk_get() when
    of_clk_get_from_provider() is called, and cleans up the clk
    structure on the error path of clk_get_sys().
    
    Fixes: 035a61c "clk: Make clk API return per-user struct clk instances"
    Reported-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
    Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
    Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
    Tested-by: Alban Browaeys <prahal@yahoo.com>
    Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
    Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
    Signed-off-by: Michael Turquette <mturquette@linaro.org>
Commits on Feb 4, 2015
  1. Mike Turquette

    clk: shmobile: div6: Avoid division by zero in .round_rate()

    Geert Uytterhoeven authored mturquette committed
    Anyone may call clk_round_rate() with a zero rate value, so we have to
    protect against that.
    
    Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
    Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
    Signed-off-by: Michael Turquette <mturquette@linaro.org>
Commits on Feb 3, 2015
  1. Stefan Wahren Mike Turquette

    clk: mxs: Fix invalid 32-bit access to frac registers

    lategoodbye authored mturquette committed
    According to i.MX23 and i.MX28 reference manual [1],[2] the fractional
    clock control register is 32-bit wide, but is separated in 4 parts.
    So write instructions must not apply to more than 1 part at once.
    
    The clk init for the i.MX28 violates this restriction and all the other
    accesses on that register suggest that there isn't such a restriction.
    
    This patch restricts the access to this register to byte instructions and
    extends the comment in the init functions.
    
    Btw the imx23 init now uses a R-M-W sequence just like imx28 init
    to avoid any clock glitches.
    
    The changes has been tested with a i.MX23 and a i.MX28 board.
    
    [1] - http://cache.freescale.com/files/dsp/doc/ref_manual/IMX23RM.pdf
    [2] - http://cache.freescale.com/files/dsp/doc/ref_manual/MCIMX28RM.pdf
    
    Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
    Reviewed-by: Marek Vasut <marex@denx.de>
    Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
    Signed-off-by: Michael Turquette <mturquette@linaro.org>
  2. arndb Mike Turquette

    clk: omap: compile legacy omap3 clocks conditionally

    arndb authored mturquette committed
    The 'ARM: OMAP3: legacy clock data move under clk driver' patch series
    causes build errors when CONFIG_OMAP3 is not set:
    
    drivers/clk/ti/dpll.c: In function 'ti_clk_register_dpll':
    drivers/clk/ti/dpll.c:199:31: error: 'omap3_dpll_ck_ops' undeclared (first use in this function)
      const struct clk_ops *ops = &omap3_dpll_ck_ops;
                                   ^
    drivers/clk/ti/dpll.c:199:31: note: each undeclared identifier is reported only once for each function it appears in
    drivers/clk/ti/dpll.c:259:10: error: 'omap3_dpll_per_ck_ops' undeclared (first use in this function)
       ops = &omap3_dpll_per_ck_ops;
              ^
    
    drivers/built-in.o: In function `ti_clk_register_gate':
    drivers/clk/ti/gate.c:179: undefined reference to `clkhwops_omap3430es2_dss_usbhost_wait'
    drivers/clk/ti/gate.c:179: undefined reference to `clkhwops_am35xx_ipss_module_wait'
    -in.o: In function `ti_clk_register_interface':
    drivers/clk/ti/interface.c:100: undefined reference to `clkhwops_omap3430es2_iclk_hsotgusb_wait'
    drivers/clk/ti/interface.c:100: undefined reference to `clkhwops_omap3430es2_iclk_dss_usbhost_wait'
    drivers/clk/ti/interface.c:100: undefined reference to `clkhwops_omap3430es2_iclk_ssi_wait'
    drivers/clk/ti/interface.c:100: undefined reference to `clkhwops_am35xx_ipss_wait'
    drivers/built-in.o: In function `ti_clk_register_composite':
    :(.text+0x3da768): undefined reference to `ti_clk_build_component_gate'
    
    In order to fix that problem, this patch makes the omap3 legacy code
    compiled only when both CONFIG_OMAP3 and CONFIG_ATAGS are set.
    
    Signed-off-by: Arnd Bergmann <arnd@arndb.de>
    Acked-by: Tony Lindgren <tony@atomide.com>
    Signed-off-by: Michael Turquette <mturquette@linaro.org>
Commits on Feb 2, 2015
  1. Mike Turquette

    Merge tag 'tegra-clk-3.20' of git://nv-tegra.nvidia.com/user/pdeschri…

    mturquette authored
    …jver/linux into clk-next
    
    Tegra clock fixes for 3.20
  2. Mike Turquette

    Merge tag 'v3.20-exynos-clk' of git://linuxtv.org/snawrocki/samsung i…

    mturquette authored
    …nto clk-next
    
    Exynos 3250, 4415 drivers cleanup by using common code
    and addition of clock definitions for DVFS on Exynos4.
  3. Tomeu Vizoso Mike Turquette

    clkdev: Export clk_register_clkdev

    tomeuv authored mturquette committed
    So it can be used from modules such as clk-test.ko.
    
    Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
    Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
    Signed-off-by: Michael Turquette <mturquette@linaro.org>
  4. Tomeu Vizoso Mike Turquette

    clk: Add rate constraints to clocks

    tomeuv authored mturquette committed
    Adds a way for clock consumers to set maximum and minimum rates. This
    can be used for thermal drivers to set minimum rates, or by misc.
    drivers to set maximum rates to assure a minimum performance level.
    
    Changes the signature of the determine_rate callback by adding the
    parameters min_rate and max_rate.
    
    Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
    Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
    [sboyd@codeaurora.org: set req_rate in __clk_init]
    Signed-off-by: Michael Turquette <mturquette@linaro.org>
    [mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate
                            migrated clk-private.h changes to clk.c]
  5. Mike Turquette

    clk: remove clk-private.h

    mturquette authored
    Private clock framework data structures should be private, surprisingly.
    
    Now that all platforms and drivers have been updated to remove static
    initializations of struct clk and struct clk_core objects and all
    references to clk-private.h have been removed we can move the
    definitions of these structures into drivers/clk/clk.c and delete the
    header.
    
    Additionally the ugly DEFINE_CLK macros have been removed. Those were
    used for static definitions of struct clk objects. That practice is no
    longer allowed.
    
    Finally __clk_init is staticized as it is no longer declared in any
    header.
    
    Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
    Signed-off-by: Michael Turquette <mturquette@linaro.org>
  6. Mike Turquette

    Merge branch 'clk-omap-legacy' into clk-next

    mturquette authored
    Conflicts:
    	arch/arm/mach-omap2/cclock3xxx_data.c
  7. Tomeu Vizoso Mike Turquette

    clk: Make clk API return per-user struct clk instances

    tomeuv authored mturquette committed
    Moves clock state to struct clk_core, but takes care to change as little API as
    possible.
    
    struct clk_hw still has a pointer to a struct clk, which is the
    implementation's per-user clk instance, for backwards compatibility.
    
    The struct clk that clk_get_parent() returns isn't owned by the caller, but by
    the clock implementation, so the former shouldn't call clk_put() on it.
    
    Because some boards in mach-omap2 still register clocks statically, their clock
    registration had to be updated to take into account that the clock information
    is stored in struct clk_core now.
    
    Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
    Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
    Tested-by: Tony Lindgren <tony@atomide.com>
    Signed-off-by: Michael Turquette <mturquette@linaro.org>
    [mturquette@linaro.org: adapted clk_has_parent to struct clk_core
                            applied OMAP3+ DPLL fix from Tero & Tony]
  8. clk: tegra: Define PLLD_DSI and remove dsia(b)_mux

    Mark Zhang authored Peter De Schrijver committed
    PLLD is the only parent for DSIA & DSIB on Tegra124 and
    Tegra132. Besides, BIT 30 in PLLD_MISC register controls
    the output of DSI clock.
    
    So this patch removes "dsia_mux" & "dsib_mux", and create
    a new clock "plld_dsi" to represent the DSI clock enable
    control.
    
    Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
    Signed-off-by: Mark Zhang <markz@nvidia.com>
  9. Paul Walmsley

    clk: tegra: Add support for the Tegra132 CAR IP block

    nvpw authored Peter De Schrijver committed
    Tegra132 CAR supports almost the same clocks as Tegra124 CAR. This
    patch mostly deals with the small differences.
    
    Since Tegra132 contains many of the same PLL clock sources used on
    Tegra114 and Tegra124, enable them in drivers/clk/tegra/clk-pll.c when
    the kernel is configured to include Tegra132 support.
    
    This patch is based on several patches from others:
    
    1. a  patch from Peter De Schrijver:
    
    http://lkml.iu.edu/hypermail/linux/kernel/1407.1/06094.html
    
    2. a patch from Bill Huang ("clk: tegra: enable cclk_g at boot on
    Tegra132"), and
    
    3. a patch from Allen Martin ("clk: Enable tegra clock driver for
    tegra132").
    
    Signed-off-by: Paul Walmsley <paul@pwsan.com>
    Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
    Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
    Cc: Allen Martin <amartin@nvidia.com>
    Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
    Cc: Stephen Warren <swarren@wwwdotorg.org>
    Cc: Thierry Reding <thierry.reding@gmail.com>
    Cc: Alexandre Courbot <gnurou@gmail.com>
    Cc: Bill Huang <bilhuang@nvidia.com>
    Cc: Mike Turquette <mturquette@linaro.org>
    Cc: Stephen Boyd <sboyd@codeaurora.org>
  10. clk: tegra: make tegra_clocks_apply_init_table() arch_initcall

    Peter De Schrijver authored
    tegra_clocks_apply_init_table() needs to be called after the udelay
    loop has been calibrated (see commit
    441f199 ("clk: tegra: defer
    application of init table") for why that is).  On existing Tegra SoCs
    this was done by calling tegra_clocks_apply_init_table() from
    tegra_dt_init(). To make this also work on ARM64, we need to change
    this into an initcall. tegra_dt_init() is called from
    customize_machine which is an arch_initcall. Therefore this should
    also work on existing 32bit Tegra SoCs.
    
    Tested on Tegra20 (ventana), Tegra30 (beaverboard), Tegra124 (jetson TK1) and
    Tegra132.
    
    Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
    [paul@pwsan.com: tweaked the commit message]
    Signed-off-by: Paul Walmsley <paul@pwsan.com>
    Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
    Cc: Thierry Reding <treding@nvidia.com>
    Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
    Cc: Mike Turquette <mturquette@linaro.org>
    Cc: Stephen Boyd <sboyd@codeaurora.org>
    Cc: Stephen Warren <swarren@wwwdotorg.org>
    Cc: Thierry Reding <thierry.reding@gmail.com>
    Cc: Alexandre Courbot <gnurou@gmail.com>
  11. Tomeu Vizoso

    clk: tegra: Fix order of arguments in WARN

    tomeuv authored Peter De Schrijver committed
    As previously the names of the present clock and its parent were swapped.
    
    Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
    Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
  12. Sean Paul

    clk: tegra124: Add init data for dsi lp clocks

    crseanpaul authored Peter De Schrijver committed
    Set the parent of the dsi lp clocks to pll_p and the rate
    to 68MHz. The default parent is clk_m and rate is 12MHz, this
    is too slow to receive data from the peripheral.
    
    Per NVidia HW engineers, the optimal rate is 70MHz, but 68MHz
    will suffice.
    
    Signed-off-by: Sean Paul <seanpaul@chromium.org>
    Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
  13. abrestic

    clk: tegra: SDMMC controllers are on APB

    abrestic authored Peter De Schrijver committed
    Since the SDMMC controller registers are accessed via the APB,
    the APB must be flushed before gating the SDMMC clocks to prevent
    register accesses to the SDMMC controllers after their clocks are
    gated.
    
    Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
    Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Commits on Jan 30, 2015
  1. Tero Kristo Mike Turquette

    clk: ti: add omap3 legacy clock data

    t-kristo authored mturquette committed
    Introduces omap3 legacy clock data under clock driver. The clock data
    is also in new format, which makes it possible to get rid of the
    clk-private.h header. This patch also introduces SoC specific init
    functions that shall be called from the low level init.
    
    The data format used in this file has two possible evolution paths;
    it can either be removed completely once no longer needed, or it will
    be possible to retain the format and modify the TI clock driver to be
    a loadable module at some point. The actual path to be followed
    will be decided later.
    
    Signed-off-by: Tero Kristo <t-kristo@ti.com>
    Acked-by: Tony Lindgren <tony@atomide.com>
    Signed-off-by: Michael Turquette <mturquette@linaro.org>
  2. Tero Kristo Mike Turquette

    clk: ti: composite: add support for legacy composite clock init

    t-kristo authored mturquette committed
    Legacy clock data is initialized slightly differently compared to
    DT clocks, thus add support for this.
    
    Signed-off-by: Tero Kristo <t-kristo@ti.com>
    Acked-by: Tony Lindgren <tony@atomide.com>
    Signed-off-by: Michael Turquette <mturquette@linaro.org>
  3. Tero Kristo Mike Turquette

    clk: ti: dpll: add support for legacy DPLL init

    t-kristo authored mturquette committed
    Legacy clock data is initialized slightly differently compared to
    DT clocks, thus add support for this.
    
    Signed-off-by: Tero Kristo <t-kristo@ti.com>
    Acked-by: Tony Lindgren <tony@atomide.com>
    Signed-off-by: Michael Turquette <mturquette@linaro.org>
  4. Tero Kristo Mike Turquette

    clk: ti: divider: add support for legacy divider init

    t-kristo authored mturquette committed
    Legacy clock data is initialized slightly differently compared to
    DT clocks, thus add support for this.
    
    Signed-off-by: Tero Kristo <t-kristo@ti.com>
    Acked-by: Tony Lindgren <tony@atomide.com>
    Signed-off-by: Michael Turquette <mturquette@linaro.org>
  5. Tero Kristo Mike Turquette

    clk: ti: interface: add support for legacy interface clock init

    t-kristo authored mturquette committed
    Legacy clock data is initialized slightly differently compared to
    DT clocks, thus add support for this. The interface clock descriptor
    itself is overloading the gate clock descriptor, thus it needs to
    be called from the gate setup.
    
    Signed-off-by: Tero Kristo <t-kristo@ti.com>
    Acked-by: Tony Lindgren <tony@atomide.com>
    Signed-off-by: Michael Turquette <mturquette@linaro.org>
  6. Tero Kristo Mike Turquette

    clk: ti: gate: add support for legacy gate init

    t-kristo authored mturquette committed
    Legacy clock data is initialialized slightly differently compared to
    DT clocks, thus add support for this.
    
    Signed-off-by: Tero Kristo <t-kristo@ti.com>
    Acked-by: Tony Lindgren <tony@atomide.com>
    Signed-off-by: Michael Turquette <mturquette@linaro.org>
  7. Tero Kristo Mike Turquette

    clk: ti: mux: add support for legacy mux init

    t-kristo authored mturquette committed
    Legacy clock data is initialized slightly differently compared to
    DT clocks, thus add support for this.
    
    Signed-off-by: Tero Kristo <t-kristo@ti.com>
    Acked-by: Tony Lindgren <tony@atomide.com>
    Signed-off-by: Michael Turquette <mturquette@linaro.org>
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