Skip to content
Utility for programming Intel/Altera Cyclone and Xilinx Serie 7
C++ VHDL Makefile Tcl
Branch: master
Clone or download
Fetching latest commit…
Cannot retrieve the latest commit at this time.
Permalink
Type Name Latest commit message Commit time
Failed to load latest commit information.
spiOverJtag
.gitignore
LICENSE
Makefile
README.md
altera.cpp
altera.hpp
bitparser.cpp
bitparser.hpp
board.hpp
cable.hpp
configBitstreamParser.cpp
configBitstreamParser.hpp
device.cpp
device.hpp
epcq.cpp
epcq.hpp
ftdijtag.cpp
ftdijtag.hpp
ftdipp_mpsse.cpp
ftdipp_mpsse.hpp
ftdispi.cpp
ftdispi.hpp
main.cpp
mcsParser.cpp
mcsParser.hpp
part.hpp
progressBar.cpp
progressBar.hpp
spiFlash.cpp
spiFlash.hpp
svf_jtag.cpp
svf_jtag.hpp
test_sfl.svf
xilinx.cpp
xilinx.hpp

README.md

cycloader

Utility for programming Intel/Altera Cyclone and Xilinx Serie 7

Current support:

  • Trenz cyc1000 Cyclone 10 LP 10CL025 (memory and spi flash)
  • Digilent arty Artix xc7a35ti (memory and spi flash)

compile and install

This application uses libftdi1, so this library must be installed (and, depending of the distribution, headers too)

apt-get install libftdi1-2 libftdi1-dev libftdipp1-3 libftdipp1-dev

and if not already done, install pkg-config, make and g++.

To build the app:

$ make

To install

$ sudo make install

Currently, the install path is hardcoded to /usr/local

Usage

cycloader --help
Usage: cycloader [OPTION...] BIT_FILE
cycloader -- a program to flash cyclone10 LP FPGA

  -b, --board=BOARD          board name, may be used instead of cable
  -c, --cable=CABLE          jtag interface
  -d, --display              display FPGA and EEPROM model
  -o, --offset=OFFSET        start offset in EEPROM
  -r, --reset                reset FPGA after operations
  -v, --verbose              Produce verbose output
  -?, --help                 Give this help list
      --usage                Give a short usage message
  -V, --version              Print program version

To have complete help

CYC1000

loading in memory:

sof to svf generation:

quartus_cpf -c -q -g 3.3 -n 12.0MHz p project_name.sof project_name.svf

file load:

cycloader -b cyc1000 project_name.svf

SPI flash:

sof to rpd:

quartus_cpf -o auto_create_rpd=on -c -d EPCQ16A -s 10CL025YU256C8G project_name.svf project_name.jic

file load:

cycloader -b cyc1000 -r project_name_auto.rpd

Note about SPI flash: svf file used to write in flash is just a bridge between FT2232 interfaceB configured in SPI mode and sfl primitive used to access EPCQ SPI flash.

Note about FT2232 interfaceB: This interface is used for SPI communication only when the dedicated svf is loaded in RAM, rest of the time, user is free to use for what he want.

ARTY

To simplify further explanations, we consider the project is generated in the current directory.

loading in memory:

.bit file is the default format generated by vivado, so nothing special task must be done to generates this bitstream.

file load:

cycloader -b arty *.runs/impl_1/*.bit

SPI flash:

.mcs must be generates through vivado with a tcl script like

set project [lindex $argv 0]

set bitfile "${project}.runs/impl_1/${project}.bit"
set mcsfile "${project}.runs/impl_1/${project}.mcs"

write_cfgmem -format mcs -interface spix4 -size 16 \
    -loadbit "up 0x0 $bitfile" -loaddata "" \
    -file $mcsfile -force

Note: -interface spix4 and -size 16 depends on SPI flash capability and size.

The tcl script is used with:

vivado -nolog -nojournal -mode batch -source script.tcl -tclargs myproject

file load:

cycloader -b arty *.runs/impl_1/*.mcs
You can’t perform that action at this time.