Cologne Chip GateMate integration #148
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This commit adds support for the Cologne Chip GateMate FPGA series. Both Evaluation Board and Programmer Cable are supported. Configurations can be loaded into the FPGA with both devices via JTAG or SPI. In addition to reading/writing data from/to flashes directly via SPI, this can also be done via the built-in JTAG-SPI-bypass. A direct wiring between programming hardware and flash is no longer necessary in this case. Signed-off-by: Patrick Urban <patrick.urban@web.de>
…GateMate and Efinix Trion T4/T8 devices
trabucayre
reviewed
Dec 12, 2021
trabucayre
reviewed
Dec 12, 2021
trabucayre
reviewed
Dec 12, 2021
trabucayre
reviewed
Dec 12, 2021
trabucayre
reviewed
Dec 12, 2021
|
LGTM! thanks! |
* add missing #include <string>
* add comment to part.hpp why highest nibble should be kept
* remove _reverseOrder variable from colognechipCfgParser.{hpp,cpp}
* rename cfgDone() to to a more meaningfull waitCfgDone()
trabucayre
reviewed
Dec 12, 2021
|
LGTM (again!)
Sorry to missed this before |
* compatibility/board.rst, compatibility/cable.rst, compatibility/fpga.rst * README.md and doc/index.rst to add new doc/vendors/colognechip.rst entry
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Sure, that was still missing. I just added this - to the best of my knowledge - and hope I didn't break anything in the >build the docs< section... |
trabucayre
reviewed
Dec 13, 2021
|
Seems ok! |
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Thanks, should be fine now |
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Applied to master! |
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This commit adds support for the Cologne Chip GateMate FPGA series.
Both Evaluation Board and Programmer Cable are supported. Configurations can be loaded into the FPGA with both devices via JTAG or SPI. In addition to reading/writing data from/to flashes directly via SPI, this can also be done via the built-in JTAG-SPI-bypass. A direct wiring between programming hardware and flash is no longer necessary in this case.
src/part.hpp. We keep the IDCODEs highest nibble to prevent confusion with Efinix T4/T8.src/cable.hppandsrc/board.hpp.src/jtag.FTDIpp_MPSSEa public parent for classFtdiJtagMPSSEso that we can access GPIO functionality.src/colognechipCfgParser.{cpp,hpp}contains the ASCII configuration parser.src/colognechip.{cpp,hpp}contains the basic functionality to write the configuration to FPGA or access external flashes via JTAG/SPI.doc/vendors/colognechip.rst.Connections of the
FT232H-based programming cable:(
ADBUS3..0configurable for SPI or JTAG communication)Connections of the
FT2232H-based evaluation board:(
ADBUS3..0is JTAG andBDBUS3..0is SPI)Note that the pin configuration for
~OE,RST,~FAILEDandDONEare valid for both evaluation board and programmer cable. I will link the official datasheets here as soon as they become available.