From a6ae85aeee37325892c3a67d57378c5acce04a17 Mon Sep 17 00:00:00 2001 From: Brad Larsen Date: Thu, 16 Apr 2020 17:04:54 -0400 Subject: [PATCH] Fix type confusion in manual CPU tests; delete dead testing code (#1669) --- tests/native/mockmem.py | 83 -------------------- tests/native/test_cpu_manual.py | 130 +++++++++++--------------------- 2 files changed, 44 insertions(+), 169 deletions(-) delete mode 100644 tests/native/mockmem.py diff --git a/tests/native/mockmem.py b/tests/native/mockmem.py deleted file mode 100644 index 9bc48aa9f..000000000 --- a/tests/native/mockmem.py +++ /dev/null @@ -1,83 +0,0 @@ -from manticore.core.smtlib import Operators - - -class Memory: # todo Mock - def getchar(self, addr): - raise NotImplementedError("getchar") - - def putchar(self, addr, value): - raise NotImplementedError("putchar") - - -class Mem: - """ Mocking class for memory """ - - def __init__(self, mem): - self.mem = dict(mem) - - def getchar(self, addr): - # print "getchar",hex(addr), "%02x"%ord(self.mem[addr]) - return self.mem[addr] - - def putchar(self, addr, char): - # print "putchar",hex(addr), "%02x"%ord(char) - self.mem[addr] = char - - def read(self, addr, size): - # print "read", hex(addr), size - result = "" - for i in range(size): - result += self.mem[addr + i] - return result - - def write(self, addr, data): - for i in range(len(data)): - self.mem[addr + i] = data[i] - - def isExecutable(self, addr): - return True - - def isWritable(self, addr): - return True - - def isReadable(self, addr): - return True - - -class SMem: - """ Mocking class for memory """ - - def __init__(self, array, init): - self.code = {} - self.mem = array - for addr, val in init.items(): - self.mem[addr] = val - - def getchar(self, addr): - if isinstance(addr, int) and addr in self.code.keys(): - return self.code[addr] - return self.mem[addr] - - def putchar(self, addr: int, char: str) -> None: - assert isinstance(addr, int) - assert isinstance(char, str) and len(char) == 1 - self.mem[addr] = char - - def read(self, addr, size): - result = [] - for i in range(size): - result.append(Operators.CHR(self.mem[addr + i])) - return result - - def write(self, addr, data): - for i in range(len(data)): - self.mem[addr + i] = data[i] - - def isExecutable(self, addr): - return True - - def isReadable(self, addr): - return True - - def isWritable(self, addr): - return True diff --git a/tests/native/test_cpu_manual.py b/tests/native/test_cpu_manual.py index 93ec891c6..853a77785 100644 --- a/tests/native/test_cpu_manual.py +++ b/tests/native/test_cpu_manual.py @@ -8,7 +8,6 @@ from manticore.native.memory import * from manticore.core.smtlib import BitVecOr, operator, Bool from manticore.core.smtlib.solver import Z3Solver -from .mockmem import Memory as MockMemory from functools import reduce from typing import List @@ -16,25 +15,6 @@ solver = Z3Solver.instance() -class ROOperand: - """ Mocking class for operand ronly """ - - def __init__(self, size, value): - self.size = size - self.value = value - - def read(self): - return self.value & ((1 << self.size) - 1) - - -class RWOperand(ROOperand): - """ Mocking class for operand rw """ - - def write(self, value): - self.value = value & ((1 << self.size) - 1) - return self.value - - sizes = { "RAX": 64, "EAX": 32, @@ -170,31 +150,6 @@ class SymCPUTest(unittest.TestCase): "IF": 0x00200, } - class ROOperand: - """ Mocking class for operand ronly """ - - def __init__(self, size, value): - self.size = size - self.value = value - - def read(self): - return self.value & ((1 << self.size) - 1) - - class RWOperand(ROOperand): - """ Mocking class for operand rw """ - - def write(self, value): - self.value = value & ((1 << self.size) - 1) - return self.value - - def setUp(self): - mem = MockMemory() - self.cpu = I386Cpu(mem) # TODO reset cpu in between tests... - # TODO mock getchar/putchar in case the instruction accesses memory directly - - def tearDown(self): - self.cpu = None - def assertItemsEqual(self, a, b): # Required for Python3 compatibility self.assertEqual(sorted(a), sorted(b)) @@ -205,7 +160,7 @@ def assertEqItems(self, a, b): return self.assertItemsEqual(a, b) def testInitialRegState(self): - cpu = self.cpu + cpu = I386Cpu(Memory32()) #'CR0', 'CR1', 'CR2', 'CR3', 'CR4', 'CR5', 'CR6', 'CR7', 'CR8', # 'DR0', 'DR1', 'DR2', 'DR3', 'DR4', 'DR5', 'DR6', 'DR7', #'MM0', 'MM1', 'MM2', 'MM3', 'MM4', 'MM5', 'MM6', 'MM7', @@ -234,7 +189,7 @@ def testInitialRegState(self): self.assertEqual(cpu.read_register(reg_name), v) def testRegisterCacheAccess(self): - cpu = self.cpu + cpu = I386Cpu(Memory32()) cpu.ESI = 0x12345678 self.assertEqual(cpu.ESI, 0x12345678) cpu.SI = 0xAAAA @@ -245,9 +200,8 @@ def testRegisterCacheAccess(self): cpu.SI = 0xAAAA self.assertEqual(cpu.SI, 0xAAAA) - def testFlagAccess(self): - - cpu = self.cpu + def testFlagAccess(self) -> None: + cpu = I386Cpu(Memory32()) cpu.RFLAGS = 0 self.assertFalse(cpu.CF) self.assertFalse(cpu.PF) @@ -341,15 +295,15 @@ def testFlagAccess(self): cpu.RFLAGS &= ~self._flags["OF"] self.assertFalse(cpu.OF) - def _check_flags_CPAZSIDO(self, c, p, a, z, s, i, d, o): - self.assertEqual(self.cpu.CF, c) - self.assertEqual(self.cpu.PF, p) - self.assertEqual(self.cpu.AF, a) - self.assertEqual(self.cpu.ZF, z) - self.assertEqual(self.cpu.SF, s) - self.assertEqual(self.cpu.IF, i) - self.assertEqual(self.cpu.DF, d) - self.assertEqual(self.cpu.OF, o) + def _check_flags_CPAZSIDO(self, cpu, c, p, a, z, s, i, d, o) -> None: + self.assertEqual(cpu.CF, c) + self.assertEqual(cpu.PF, p) + self.assertEqual(cpu.AF, a) + self.assertEqual(cpu.ZF, z) + self.assertEqual(cpu.SF, s) + self.assertEqual(cpu.IF, i) + self.assertEqual(cpu.DF, d) + self.assertEqual(cpu.OF, o) def _construct_flag_bitfield(self, flags): return reduce(operator.or_, (self._flags[f] for f in flags)) @@ -357,24 +311,26 @@ def _construct_flag_bitfield(self, flags): def _construct_sym_flag_bitfield(self, flags): return reduce(operator.or_, (BitVecConstant(32, self._flags[f]) for f in flags)) - def test_set_eflags(self): - self.assertEqual(self.cpu.EFLAGS, 0) + def test_set_eflags(self) -> None: + cpu = I386Cpu(Memory32()) + self.assertEqual(cpu.EFLAGS, 0) flags = ["CF", "PF", "AF", "ZF", "SF"] - self.cpu.EFLAGS = self._construct_flag_bitfield(flags) + cpu.EFLAGS = self._construct_flag_bitfield(flags) - self._check_flags_CPAZSIDO(1, 1, 1, 1, 1, 0, 0, 0) + self._check_flags_CPAZSIDO(cpu, 1, 1, 1, 1, 1, 0, 0, 0) - def test_get_eflags(self): - self.assertEqual(self.cpu.EFLAGS, 0) + def test_get_eflags(self) -> None: + cpu = I386Cpu(Memory32()) + self.assertEqual(cpu.EFLAGS, 0) flags = ["CF", "AF", "SF"] - self.cpu.CF = 1 - self.cpu.AF = 1 - self.cpu.SF = 1 - self.cpu.DF = 0 + cpu.CF = 1 + cpu.AF = 1 + cpu.SF = 1 + cpu.DF = 0 - self.assertEqual(self.cpu.EFLAGS, self._construct_flag_bitfield(flags)) + self.assertEqual(cpu.EFLAGS, self._construct_flag_bitfield(flags)) def test_set_sym_eflags(self): def check_flag(obj, flag): @@ -386,12 +342,13 @@ def check_flag(obj, flag): flags = ["CF", "PF", "AF", "ZF"] sym_bitfield = self._construct_sym_flag_bitfield(flags) - self.cpu.EFLAGS = sym_bitfield + cpu = I386Cpu(Memory32()) + cpu.EFLAGS = sym_bitfield - check_flag(self.cpu.CF, "CF") - check_flag(self.cpu.PF, "PF") - check_flag(self.cpu.AF, "AF") - check_flag(self.cpu.ZF, "ZF") + check_flag(cpu.CF, "CF") + check_flag(cpu.PF, "PF") + check_flag(cpu.AF, "AF") + check_flag(cpu.ZF, "ZF") def test_get_sym_eflags(self): def flatten_ors(x: BitVecOr) -> List: @@ -410,26 +367,27 @@ def flatten_ors(x: BitVecOr) -> List: else: return list(x.operands) - self.cpu.CF = 1 - self.cpu.AF = 1 + cpu = I386Cpu(Memory32()) + cpu.CF = 1 + cpu.AF = 1 a = BitVecConstant(32, 1) != 0 b = BitVecConstant(32, 0) != 0 - self.cpu.ZF = a - self.cpu.SF = b + cpu.ZF = a + cpu.SF = b - flags = flatten_ors(self.cpu.EFLAGS) + flags = flatten_ors(cpu.EFLAGS) - self.assertTrue(isinstance(self.cpu.EFLAGS, BitVecOr)) + self.assertTrue(isinstance(cpu.EFLAGS, BitVecOr)) self.assertEqual(len(flags), 8) - self.assertEqual(self.cpu.CF, 1) - self.assertEqual(self.cpu.AF, 1) - self.assertIs(self.cpu.ZF, a) - self.assertIs(self.cpu.SF, b) + self.assertEqual(cpu.CF, 1) + self.assertEqual(cpu.AF, 1) + self.assertIs(cpu.ZF, a) + self.assertIs(cpu.SF, b) def testRegisterAccess(self): - cpu = self.cpu + cpu = I386Cpu(Memory32()) # initially zero self.assertEqual(cpu.EAX, 0)