From 8f17c1fdd46fa498fa7ea947b2cfa55699c8b17a Mon Sep 17 00:00:00 2001 From: disconnect3d Date: Thu, 20 Dec 2018 16:48:33 +0100 Subject: [PATCH 1/3] Speed up ArmV7Operand.type assertions So .type will now just return the value instead of building a mapping and returning a result. --- manticore/native/cpu/arm.py | 50 +++++++++++++++++++++---------------- 1 file changed, 28 insertions(+), 22 deletions(-) diff --git a/manticore/native/cpu/arm.py b/manticore/native/cpu/arm.py index c483279d9..8d616bb09 100644 --- a/manticore/native/cpu/arm.py +++ b/manticore/native/cpu/arm.py @@ -53,25 +53,30 @@ def instruction_implementation(cpu, *args, **kwargs): return abstract_instruction(instruction_implementation) +_TYPE_MAP = { + cs.arm.ARM_OP_REG: 'register', + cs.arm.ARM_OP_MEM: 'memory', + cs.arm.ARM_OP_IMM: 'immediate', + cs.arm.ARM_OP_PIMM: 'coprocessor', + cs.arm.ARM_OP_CIMM: 'immediate' +} + + class Armv7Operand(Operand): def __init__(self, cpu, op, **kwargs): super().__init__(cpu, op, **kwargs) + self.__type = _TYPE_MAP[self.op.type] @property def type(self): - type_map = { - cs.arm.ARM_OP_REG: 'register', - cs.arm.ARM_OP_MEM: 'memory', - cs.arm.ARM_OP_IMM: 'immediate', - cs.arm.ARM_OP_PIMM: 'coprocessor', - cs.arm.ARM_OP_CIMM: 'immediate' - } - - return type_map[self.op.type] + """ + Corresponds to capstone's `operand.type` (cs.arm.RAM_OP_*). + """ + return self.__type @property def size(self): - assert self.type == 'register' + assert self.__type == 'register' if cs.arm.ARM_REG_D0 <= self.op.reg <= cs.arm.ARM_REG_D31: return 64 else: @@ -80,7 +85,7 @@ def size(self): def read(self, nbits=None, with_carry=False): carry = self.cpu.regfile.read('APSR_C') - if self.type == 'register': + if self.__type == 'register': value = self.cpu.regfile.read(self.reg) # PC in this case has to be set to the instruction after next. PC at this point # is already pointing to next instruction; we bump it one more. @@ -94,17 +99,17 @@ def read(self, nbits=None, with_carry=False): if with_carry: return value, carry return value - elif self.type == 'immediate': + elif self.__type == 'immediate': imm = self.op.imm if self.op.subtracted: imm = -imm if with_carry: return imm, self._get_expand_imm_carry(carry) return imm - elif self.type == 'coprocessor': + elif self.__type == 'coprocessor': imm = self.op.imm return imm - elif self.type == 'memory': + elif self.__type == 'memory': val = self.cpu.read_int(self.address(), nbits) if with_carry: return val, carry @@ -113,17 +118,17 @@ def read(self, nbits=None, with_carry=False): raise NotImplementedError("readOperand unknown type", self.op.type) def write(self, value, nbits=None): - if self.type == 'register': + if self.__type == 'register': self.cpu.regfile.write(self.reg, value) - elif self.type == 'memory': + elif self.__type == 'memory': raise NotImplementedError('need to impl arm store mem') else: raise NotImplementedError("writeOperand unknown type", self.op.type) def writeback(self, value): - if self.type == 'register': + if self.__type == 'register': self.write(value) - elif self.type == 'memory': + elif self.__type == 'memory': self.cpu.regfile.write(self.mem.base, value) else: raise NotImplementedError("writeback Operand unknown type", self.op.type) @@ -141,15 +146,16 @@ def is_shifted(self): :return: True if operand is shifted, otherwise False. """ - return self.op.shift.type != cs.arm.ARM_SFT_INVALID + return self.op.mem.lshift != 0 + # return self.op.shift.type != cs.arm.ARM_SFT_INVALID def address(self): - assert self.type == 'memory' + assert self.__type == 'memory' addr = self.get_mem_base_addr() + self.get_mem_offset() return addr & Mask(self.cpu.address_bit_size) def get_mem_offset(self): - assert self.type == 'memory' + assert self.__type == 'memory' off = 0 if self.mem.index is not None: @@ -164,7 +170,7 @@ def get_mem_offset(self): return off def get_mem_base_addr(self): - assert self.type == 'memory' + assert self.__type == 'memory' base = self.cpu.regfile.read(self.mem.base) From 4eb871818727e9135beb9759dddc455888f9cca3 Mon Sep 17 00:00:00 2001 From: Disconnect3d Date: Thu, 20 Dec 2018 16:50:24 +0100 Subject: [PATCH 2/3] Update manticore/native/cpu/arm.py --- manticore/native/cpu/arm.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/manticore/native/cpu/arm.py b/manticore/native/cpu/arm.py index 8d616bb09..85d8d0807 100644 --- a/manticore/native/cpu/arm.py +++ b/manticore/native/cpu/arm.py @@ -70,7 +70,7 @@ def __init__(self, cpu, op, **kwargs): @property def type(self): """ - Corresponds to capstone's `operand.type` (cs.arm.RAM_OP_*). + Corresponds to capstone's `operand.type` (cs.arm.ARM_OP_*). """ return self.__type From 97b0629d8e6e6984a81fede8354df6e8abebeb80 Mon Sep 17 00:00:00 2001 From: disconnect3d Date: Thu, 20 Dec 2018 16:51:12 +0100 Subject: [PATCH 3/3] Revert debug changes --- manticore/native/cpu/arm.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/manticore/native/cpu/arm.py b/manticore/native/cpu/arm.py index 8d616bb09..187fa8af5 100644 --- a/manticore/native/cpu/arm.py +++ b/manticore/native/cpu/arm.py @@ -146,8 +146,7 @@ def is_shifted(self): :return: True if operand is shifted, otherwise False. """ - return self.op.mem.lshift != 0 - # return self.op.shift.type != cs.arm.ARM_SFT_INVALID + return self.op.shift.type != cs.arm.ARM_SFT_INVALID def address(self): assert self.__type == 'memory'