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Connectal is a framework for software-driven hardware development.
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Riscy Processors - Open-Sourced RISC-V Processors
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P4-14/16 Bluespec Compiler
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The BERI and CHERI processor and hardware platform
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RiscyOO: RISC-V Out-of-Order Processor
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Open Source SSD Controller. NVMe and Lightstor variants
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A generic test bench written in Bluespec
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MAERI public release
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A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
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Bluespec BSV HLHDL tutorial
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OGC Points of Interest Encoding Specification
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RISC-V BSV Specification
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Bluespec SystemVerilog library for use of the IBM Coherent Accelerator-Processor Interface (CAPI)
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Public release
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Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework
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Bluespec SystemVerilog Reed Solomon Decoder
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P4FPGA is located at github.com/hanw/p4fpga
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MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
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Structural Spec parser based on Bluespec
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Bluespec System Verilog language extension for Visual Studio Code
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A Network Architecture for Disaggregated Racks
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LEAP FPGA primary components
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Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
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Bluespec H.264 Decoder
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Bluespec 802.11a Transmitter
