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Ariane is a 6-stage RISC-V CPU capable of booting Linux
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A directory of Western Digital’s RISC-V SweRV Cores
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RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
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Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
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The root repo for lowRISC project and FPGA demos.
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An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.
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A Verilog synthesis flow for Minecraft redstone circuits
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SCR1 is a high-quality open-source RISC-V MCU core in Verilog
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RISC-V CPU Core
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training labs and examples
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Contains the code examples from The UVM Primer Book sorted by chapters.
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CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
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Reference examples and short projects using UVM Methodology
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This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
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Ultimate multigame cartridge for Nintendo Famicom
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This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
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Source code repo for UVM Tutorial for Candy Lovers
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Verilog code for a simple synth module; developed on TinyFPGA BX
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Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
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Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
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a playground for xilinx zynq fpga experiments
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High performance embedded systems debug/reverse engineering platform
