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Trending in open source

See what the GitHub community is most excited about this month.

  1. genome / pindel

    Pindel can detect breakpoints of large deletions, medium sized insertions, inversions, tandem duplications and other structural variants at single-based resolution from next-gen sequence data. It uses a pattern growth approach to identify the breakpoints of these variants from paired-end short reads.

    SystemVerilog • Built by @liangkaiye @EWLameijer @jmarshall @nnutter @mkroon1

  2. lowRISC / lowrisc-chip

    The root repo for lowRISC project and FPGA demos.

    SystemVerilog • Built by @wsong83 @wallento

  3. rdsalemi / uvmprimer

    Contains the code examples from The UVM Primer Book sorted by chapters.

    SystemVerilog • Built by @rdsalemi

  4. VerificationExcellence / SystemVerilogReference

    training labs and examples

    SystemVerilog • Built by @mramdas

  5. swetland / zynq-sandbox

    a playground for xilinx zynq fpga experiments

    SystemVerilog • Built by @swetland @travisg

  6. VerificationExcellence / UVMReference

    Reference examples and short projects using UVM Methodology

    SystemVerilog • Built by @mramdas @robingarg89

  7. pulp-platform / riscv

    SystemVerilog • Built by @atraber @svenstucki @FrancescoConti @be4web

  8. unihd-cag / openhmc

    openHMC - an open source Hybrid Memory Cube Controller

    SystemVerilog • Built by @jurischmidt

  9. VerificationExcellence / SystemVerilogAssertions

    Examples and reference for System Verilog Assertions

    SystemVerilog • Built by @mramdas

  10. ClusterM / coolgirl-famicom-multicard

    Ultimate multigame cartridge for Nintendo Famicom

    SystemVerilog • Built by @ClusterM

  11. nosnhojn / svunit-code

    SystemVerilog • Built by @nosnhojn @tudortimi @daveread4

  12. cluelogic / uvm-tutorial-for-candy-lovers

    Source code repo for UVM Tutorial for Candy Lovers

    SystemVerilog • Built by @cluelogic

  13. Poofjunior / fpga_fast_serial_sort

    a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially

    SystemVerilog • Built by @Poofjunior

  14. amiq-consulting / svaunit

    SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)

    SystemVerilog • Built by @amiq-consulting

  15. nosnhojn / uvm-utest

    SystemVerilog • Built by @nosnhojn @kgover

  16. dovstamler / uvm_agents

    UVM agents

    SystemVerilog • Built by @dovstamler

  17. melt-umn / silver

    An attribute grammar-based meta-programming language for composable language extensions

    SystemVerilog • Built by @tedinski @ericvanwyk @krame505 @charleshofer @kambamsu

  18. cjdrake / AES

    Advanced Encryption Standard (AES) SystemVerilog Core

    SystemVerilog • Built by @cjdrake

  19. amiq-consulting / amiq_apb

    SystemVerilog VIP for AMBA APB protocol

    SystemVerilog • Built by @amiq-consulting

  20. RoaLogic / adv_dbg_if

    Universal Advanced JTAG Debug Interface

    SystemVerilog • Built by @rherveille

  21. luuvish / system-verilog-patterns

    SystemVerilog Design Patterns

    SystemVerilog • Built by @luuvish

  22. UCLONG / NetEmulation

    Software Simulation and Hardware Synthesis of Electrical and Optical Interconnection Networks

    SystemVerilog • Built by @DannyNicholls @BorisDosen @pmwatts @ridwanmadarbux @p-andreades

  23. amiq-consulting / amiq_eth

    Library defining all Ethernet packets in SystemVerilog and in SystemC

    SystemVerilog • Built by @amiq-consulting

  24. pbing / USB

    FPGA USB 1.1 Implementation

    SystemVerilog • Built by @pbing

  25. jeras / rp8

    RISC processor 8bit (AVR ISA), RTL based on 'navre'

    SystemVerilog • Built by @jeras

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