Trending in open source

See what the GitHub community is most excited about this month.

  1. parallella / oh

    Silicon proven Verilog library for IC and FPGA designers

    Verilog • 13 stars this month • Built by @aolofsson @olajep @peteasa @Fred3 @plindstroem

  2. analogdevicesinc / hdl

    HDL libraries and projects

    Verilog • 8 stars this month • Built by @rkutty @Csomi @acostina @larsclausen @mhennerich

  3. ucb-bar / fpga-zynq

    Support for Rocket Chip on Zynq FPGAs

    Verilog • Built by @sbeamer @sagark @davidbiancolin @xfguo @arunthomas

  4. EttusResearch / fpga

    The USRP™ Hardware Driver FPGA Repository

    Verilog • Built by @MattEttus @achaudhari @guruofquality @mfischer @michael-west

  5. VerticalResearchGroup / miaow

    An open source GPU based off of the AMD Southern Islands ISA.

    Verilog • Built by @zwabbit @d1duarte @vinaygangadhar @stanso @tchamberlain71

  6. cliffordwolf / picorv32

    PicoRV32 - A Size-Optimized RISC-V CPU

    Verilog • Built by @cliffordwolf @olofk @neuschaefer @ldoolitt

  7. kramble / FPGA-Litecoin-Miner

    A litecoin scrypt miner implemented with FPGA on-chip memory.

    Verilog • Built by @kramble @C-Elegans

  8. zhemao / ez8

    The Easy 8-bit Processor

    OCaml • Built by @zhemao

  9. marmolejo / zet

    Open source implementation of a x86 processor

    Verilog • Built by @marmolejo @sirchuckalot @ys05 @AlteraFreak

  10. openrisc / mor1kx

    mor1kx - an OpenRISC 1000 processor IP core

    Verilog • Built by @skristiansson @juliusbaxter @wallento @enjoy-digital @olofk

  11. NetFPGA / netfpga

    NetFPGA 1G infrastructure and gateware

    Verilog • Built by @grg @ericklo @divinekumar @rkerur @eastzone

  12. m-labs / milkymist

    SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU

    Verilog • Built by @sbourdeauducq @wpwrak @mwalle @tmatsuya @xiangfu

  13. gardners / c65gs

    FPGA-based C64 Accelerator / C65 like computer

    Verilog • Built by @gardners @Blaizer @justburn

  14. jmahler / mips-cpu

    MIPS CPU implemented in Verilog

    Verilog • Built by @jmahler

  15. brianbennett / fpga_nes

    FPGA-based Nintendo Entertainment System Emulator

    Verilog • Built by @brianbennett

  16. Arlet / verilog-6502

    A Verilog HDL model of the MOS 6502 CPU

    Verilog • Built by @Arlet

  17. ngzhang / Icarus

    DUAL Spartan6 Development Platform

    Verilog • Built by @ngzhang @xiangfu

  18. jamieiles / oldland-cpu

    Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

    Verilog • Built by @jamieiles

  19. andrejbauer / Homotopy

    Homotopy theory in Coq.

    Verilog • Built by @andrejbauer @peterlefanulumsdaine

  20. openrisc / orpsoc-cores

    Core description files for FuseSoC

    Verilog • Built by @olofk @skristiansson @fjullien @bluecmd @hansfbaier

  21. dtysky / FPGA-Imaging-Library

    An open source library for image processing on FPGA.

    Verilog • Built by @dtysky

  22. strigeus / fpganes

    NES in Verilog

    Verilog • Built by @strigeus

  23. Obijuan / open-fpga-verilog-tutorial

    Aprender a diseñar sistemas digitales sintetizables en FPGAs usando SOLO herramientas libres #verilog #icestorm #lattice #Linux

    Verilog • Built by @Obijuan @Testato @Jesus89 @ZioGuillo @dcuartielles

  24. veripool / verilog-mode

    Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

    Verilog • Built by @wsnyder @MichaelTYMcNamara @acr4 @eggert @kaushalmodi

  25. m-labs / lm32

    LatticeMico32 soft processor

    Verilog • Built by @mwalle @terpstra @fallen @sbourdeauducq @cliffordwolf

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