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  1. A work-in-progress for what is to be a software-free web server for static content.

    VHDL 679 21 Built by @hamsternz @JsWatt
  2. A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able p…

    VHDL 594 314 Built by @fpgaminer @IAmNotDorian @teknohog @progranism @makomk
  3. Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

    VHDL 432 96 Built by @kristopk @AWSGH @AWSwinefred @AWSNB @deeppat
  4. GPL v3 2D/3D graphics engine in verilog

    VHDL 349 63 Built by @asicguy
  5. Community created parallella projects

    VHDL 339 124 Built by @olajep @aolofsson @wizard97 @9600 @DonQuichotteComputers
  6. Parallella board design files

    VHDL 336 155 Built by @aolofsson @avivbur @olofk @oz-shmueli
  7. VHDL 2008/93/87 simulator

    VHDL 321 65 Built by @tgingold @gingold-adacore @Brian-Drummond @Paebbels @1138-4EB
  8. GameCube Digital AV converter

    VHDL 182 30 Built by @ikorb
  9. Core sources and tools for the MIST board

    VHDL 174 27 Built by @harbaum @renaudhelias @wsoltys @Newsdee @sebdel
  10. VUnit is a unit testing framework for VHDL/SystemVerilog

    VHDL 146 53 Built by @kraigher @LarsAsplund @joshrsmith @cmarqu @go2sh
  11. Arduino MIPI DSI Shield

    VHDL 146 48 Built by @twlostow
  12. IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

    VHDL 131 28 Built by @Paebbels @preusser @mzabeltud @krabo0om @vossy454
  13. Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer

    VHDL 120 19 Built by @gtaylormb @stohrendorf
  14. A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able p…

    VHDL 119 314 Built by @fpgaminer @IAmNotDorian @teknohog @progranism @makomk
  15. RISC-V by VectorBlox

    VHDL 118 30 Built by @vanjoe @rdeiaco @prashantrar
  16. Space Invaders game implemented with VHDL

    VHDL 113 8 Built by @fabioperez
  17. A 32-bit RISC-V / MIPS ISA retargetable CPU core

    VHDL 102 49 Built by @gornjas @emard @goran-mahovlic @XarkLabs @ojura
  18. An implementation of DisplayPort protocol for FPGAs

    VHDL 97 16 Built by @hamsternz @pwolf23
  19. Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project

    VHDL 96 25 Built by @mithro @shenki @ajitmathew @makestuff @jahanzeb
  20. FPGA-based HDMI ambient lighting

    VHDL 78 18 Built by @drxzcl
  21. A pipelined RISCV implementation in VHDL

    VHDL 76 11 Built by @inforichland @cHemingway
  22. Yet Another Forth Core...

    VHDL 67 3 Built by @inforichland
  23. ZPUino HDL implementation

    VHDL 64 42 Built by @alvieboy @jackgassett @mhaghighi @devbisme @oharboe
  24. The Zylin ZPU

    VHDL 60 16 Built by @bert-lange @oharboe @alvieboy
  25. A repository of IPs for hardware computer vision (FPGA)

    VHDL 57 30 Built by @jpiat @peepo
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