Trending in open source

See what the GitHub community is most excited about this month.

  1. A version of the HDMI2USB firmware based around LiteX tools produced by @Enjoy-Digital (based on misoc+migen created by @M-Labs)

    VHDL 40 30 Built by @mithro @enjoy-digital @shenki @xfxf @joeladdison
  2. A work-in-progress for what is to be a software-free web server for static content.

    VHDL 661 18 Built by @hamsternz @JsWatt
  3. A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able p…

    VHDL 497 259 Built by @fpgaminer @IAmNotDorian @teknohog @progranism @makomk
  4. GPL v3 2D/3D graphics engine in verilog

    VHDL 326 58 Built by @asicguy
  5. Parallella board design files

    VHDL 315 148 Built by @aolofsson @avivbur @olofk @oz-shmueli
  6. Community created parallella projects

    VHDL 303 112 Built by @olajep @aolofsson @wizard97 @9600 @DonQuichotteComputers
  7. VHDL 2008/93/87 simulator

    VHDL 239 50 Built by @tgingold @gingold-adacore @Brian-Drummond @Paebbels @1138-4EB
  8. GameCube Digital AV converter

    VHDL 147 26 Built by @ikorb
  9. Core sources and tools for the MIST board

    VHDL 145 21 Built by @harbaum @renaudhelias @wsoltys @Newsdee @sebdel
  10. Arduino MIPI DSI Shield

    VHDL 120 40 Built by @twlostow
  11. VUnit is a unit testing framework for VHDL/SystemVerilog

    VHDL 119 40 Built by @kraigher @LarsAsplund @joshrsmith @cmarqu @go2sh
  12. A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able p…

    VHDL 113 259 Built by @fpgaminer @IAmNotDorian @teknohog @progranism @makomk
  13. Space Invaders game implemented with VHDL

    VHDL 107 5 Built by @fabioperez
  14. Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer

    VHDL 98 12 Built by @gtaylormb @stohrendorf
  15. Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project

    VHDL 94 24 Built by @mithro @shenki @ajitmathew @makestuff @jahanzeb
  16. RISC-V by VectorBlox

    VHDL 94 20 Built by @vanjoe @prashantrar
  17. IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

    VHDL 89 20 Built by @Paebbels @preusser @mzabeltud @krabo0om @vossy454
  18. An implementation of DisplayPort protocol for FPGAs

    VHDL 86 12 Built by @hamsternz @pwolf23
  19. A pipelined RISCV implementation in VHDL

    VHDL 73 9 Built by @inforichland @cHemingway
  20. FPGA-based HDMI ambient lighting

    VHDL 70 15 Built by @drxzcl
  21. Yet Another Forth Core...

    VHDL 67 3 Built by @inforichland
  22. A 32-bit RISC-V / MIPS retargetable CPU core

    VHDL 66 35 Built by @gornjas @emard @goran-mahovlic @XarkLabs @ojura
  23. ZPUino HDL implementation

    VHDL 58 41 Built by @alvieboy @jackgassett @mhaghighi @devbisme @oharboe
  24. A repository of IPs for hardware computer vision (FPGA)

    VHDL 53 26 Built by @jpiat @peepo
  25. The Zylin ZPU

    VHDL 47 10 Built by @bert-lange @oharboe @alvieboy
ProTip! Looking for most forked VHDL repositories? Try this search