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MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
SystemVerilog Verilog Assembly C C++ Objective-C Other
Branch: master
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Latest commit c029e7e Apr 30, 2019
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doc Fix typo in doc Aug 20, 2018
software @ 63cb05a Update to latest bootloader Apr 29, 2019
src Fix a stupid typo in clz. Apr 29, 2019
testbench Update llsc testcase. Apr 28, 2019
vivado Merge branch 'master' of git.tsinghua.edu.cn:chensq16/TrivialMIPS Apr 29, 2019
.gitlab-ci.yml Fix permission problem of checking script (again), add sim dir to CI … Oct 14, 2018
.gitmodules Update submodule git url Mar 21, 2019
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