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Fix interrupt handling from the APB periperals (ie, UART) - it

also requires an explicit acknowledgement.

Tested:

* AR9344 (DB120) SoC

Approved by:	re@ (gjb)
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1 parent 6a646a0 commit 543de26f07ddbb8da0e52ec7e211ed685464132c adrian committed Oct 9, 2013
Showing with 3 additions and 0 deletions.
  1. +3 −0 sys/mips/atheros/apb.c
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@@ -359,6 +359,9 @@ apb_filter(void *arg)
case AR71XX_SOC_AR7242:
case AR71XX_SOC_AR9330:
case AR71XX_SOC_AR9331:
+ case AR71XX_SOC_AR9341:
+ case AR71XX_SOC_AR9342:
+ case AR71XX_SOC_AR9344:
/* Ack/clear the irq on status register for AR724x */
ATH_WRITE_REG(AR71XX_MISC_INTR_STATUS,
reg & ~(1 << irq));

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