Please sign in to comment.
Merge projects/bhyve_npt_pmap into head.
Make the amd64/pmap code aware of nested page table mappings used by bhyve guests. This allows bhyve to associate each guest with its own vmspace and deal with nested page faults in the context of that vmspace. This also enables features like accessed/dirty bit tracking, swapping to disk and transparent superpage promotions of guest memory. Guest vmspace: Each bhyve guest has a unique vmspace to represent the physical memory allocated to the guest. Each memory segment allocated by the guest is mapped into the guest's address space via the 'vmspace->vm_map' and is backed by an object of type OBJT_DEFAULT. pmap types: The amd64/pmap now understands two types of pmaps: PT_X86 and PT_EPT. The PT_X86 pmap type is used by the vmspace associated with the host kernel as well as user processes executing on the host. The PT_EPT pmap is used by the vmspace associated with a bhyve guest. Page Table Entries: The EPT page table entries as mostly similar in functionality to regular page table entries although there are some differences in terms of what bits are used to express that functionality. For e.g. the dirty bit is represented by bit 9 in the nested PTE as opposed to bit 6 in the regular x86 PTE. Therefore the bitmask representing the dirty bit is now computed at runtime based on the type of the pmap. Thus PG_M that was previously a macro now becomes a local variable that is initialized at runtime using 'pmap_modified_bit(pmap)'. An additional wrinkle associated with EPT mappings is that older Intel processors don't have hardware support for tracking accessed/dirty bits in the PTE. This means that the amd64/pmap code needs to emulate these bits to provide proper accounting to the VM subsystem. This is achieved by using the following mapping for EPT entries that need emulation of A/D bits: Bit Position Interpreted By PG_V 52 software (accessed bit emulation handler) PG_RW 53 software (dirty bit emulation handler) PG_A 0 hardware (aka EPT_PG_RD) PG_M 1 hardware (aka EPT_PG_WR) The idea to use the mapping listed above for A/D bit emulation came from Alan Cox (alc@). The final difference with respect to x86 PTEs is that some EPT implementations do not support superpage mappings. This is recorded in the 'pm_flags' field of the pmap. TLB invalidation: The amd64/pmap code has a number of ways to do invalidation of mappings that may be cached in the TLB: single page, multiple pages in a range or the entire TLB. All of these funnel into a single EPT invalidation routine called 'pmap_invalidate_ept()'. This routine bumps up the EPT generation number and sends an IPI to the host cpus that are executing the guest's vcpus. On a subsequent entry into the guest it will detect that the EPT has changed and invalidate the mappings from the TLB. Guest memory access: Since the guest memory is no longer wired we need to hold the host physical page that backs the guest physical page before we can access it. The helper functions 'vm_gpa_hold()/vm_gpa_release()' are available for this purpose. PCI passthru: Guest's with PCI passthru devices will wire the entire guest physical address space. The MMIO BAR associated with the passthru device is backed by a vm_object of type OBJT_SG. An IOMMU domain is created only for guest's that have one or more PCI passthru devices attached to them. Limitations: There isn't a way to map a guest physical page without execute permissions. This is because the amd64/pmap code interprets the guest physical mappings as user mappings since they are numerically below VM_MAXUSER_ADDRESS. Since PG_U shares the same bit position as EPT_PG_EXECUTE all guest mappings become automatically executable. Thanks to Alan Cox and Konstantin Belousov for their rigorous code reviews as well as their support and encouragement. Thanks for John Baldwin for reviewing the use of OBJT_SG as the backing object for pci passthru mmio regions. Special thanks to Peter Holm for testing the patch on short notice. Approved by: re Discussed with: grehan Reviewed by: alc, kib Tested by: pho
- Loading branch information...
Showing with 2,113 additions and 862 deletions.
- +24 −1 lib/libvmmapi/vmmapi.c
- +3 −1 lib/libvmmapi/vmmapi.h
- +1 −1 sys/amd64/amd64/machdep.c
- +916 −137 sys/amd64/amd64/pmap.c
- +10 −1 sys/amd64/amd64/trap.c
- +89 −26 sys/amd64/include/pmap.h
- +30 −13 sys/amd64/include/vmm.h
- +11 −1 sys/amd64/include/vmm_dev.h
- +4 −0 sys/amd64/include/vmm_instruction_emul.h
- +21 −22 sys/amd64/vmm/amd/amdv.c
- +54 −250 sys/amd64/vmm/intel/ept.c
- +4 −8 sys/amd64/vmm/intel/ept.h
- +2 −3 sys/amd64/vmm/intel/vmcs.c
- +12 −1 sys/amd64/vmm/intel/vmcs.h
- +105 −70 sys/amd64/vmm/intel/vmx.c
- +14 −2 sys/amd64/vmm/intel/vmx.h
- +9 −0 sys/amd64/vmm/intel/vmx_genassym.c
- +82 −7 sys/amd64/vmm/intel/vmx_support.S
- +38 −8 sys/amd64/vmm/io/ppt.c
- +10 −4 sys/amd64/vmm/io/ppt.h
- +490 −174 sys/amd64/vmm/vmm.c
- +33 −27 sys/amd64/vmm/vmm_dev.c
- +15 −13 sys/amd64/vmm/vmm_instruction_emul.c
- +80 −61 sys/amd64/vmm/vmm_mem.c
- +8 −2 sys/amd64/vmm/vmm_mem.h
- +13 −15 usr.sbin/bhyve/bhyverun.c
- +1 −1 usr.sbin/bhyve/pci_emul.c
- +2 −2 usr.sbin/bhyve/rtc.c
- +30 −9 usr.sbin/bhyvectl/bhyvectl.c
- +2 −2 usr.sbin/bhyveload/bhyveload.c
Oops, something went wrong.