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move cpu clock to the top level module to facilitate debug stepping

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commit 9e2b80f33ee55cd03e192282f7a0b321cce347a7 1 parent 805cede
@trun authored
Showing with 41 additions and 37 deletions.
  1. +1 −1  data/boot.rom
  2. +5 −29 gameboy.v
  3. +35 −7 s6atlys.v
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2  data/boot.rom
@@ -253,4 +253,4 @@ FE
3E
01
E0
-50
+50
View
34 gameboy.v
@@ -3,6 +3,7 @@
module gameboy (
input wire clock,
+ input wire cpu_clock,
input wire reset,
input wire reset_init,
@@ -44,7 +45,10 @@ module gameboy (
output wire [15:0] AF,
output wire [15:0] BC,
output wire [15:0] DE,
- output wire [15:0] HL
+ output wire [15:0] HL,
+ output wire [15:0] A_cpu,
+ output wire [7:0] Di_cpu,
+ output wire [7:0] Do_cpu
);
//assign pixel_data = 2'b0;
@@ -62,9 +66,6 @@ module gameboy (
wire reset_n, wait_n, int_n, nmi_n, busrq_n; // cpu inputs
wire m1_n, mreq_n, iorq_n, rd_cpu_n, wr_cpu_n, rfsh_n, halt_n, busak_n; // cpu outputs
- wire [15:0] A_cpu;
- wire [7:0] Di_cpu;
- wire [7:0] Do_cpu;
//
// Debug - CPU I/O Pins
@@ -82,15 +83,6 @@ module gameboy (
};
//
- // CPU clock
- //
-
- reg [2:0] clock_divider; // overflows every 8 cycles
-
- wire cpu_clock;
- BUFG cpu_clock_buf(.I(clock_divider[2]), .O(cpu_clock));
-
- //
// CPU internal registers
//
@@ -299,21 +291,5 @@ module gameboy (
.button_sel(joypad_sel),
.button_data(joypad_data)
);
-
- //
- // Advance CPU Clock
- //
-
- always @(posedge clock)
- begin
- if (reset_init)
- begin
- clock_divider <= 0;
- end
- else
- begin
- clock_divider <= clock_divider + 1;
- end
- end
endmodule
View
42 s6atlys.v
@@ -90,6 +90,15 @@ module s6atlys(
);
//
+ // CPU clock - overflows every 8 cycles
+ //
+
+ reg [2:0] clock_divider;
+
+ wire cpu_clock;
+ BUFG cpu_clock_buf(.I(clock_divider[2]), .O(cpu_clock));
+
+ //
// Switches
//
// SW0-SW4 - Breakpoints Switches (Not Implemented)
@@ -162,9 +171,13 @@ module s6atlys(
wire [15:0] BC;
wire [15:0] DE;
wire [15:0] HL;
+ wire [15:0] A_cpu;
+ wire [7:0] Di_cpu;
+ wire [7:0] Do_cpu;
gameboy gameboy (
.clock(clock),
+ .cpu_clock(cpu_clock),
.reset(reset),
.reset_init(reset_init),
.A(A),
@@ -195,14 +208,17 @@ module s6atlys(
.AF(AF),
.BC(BC),
.DE(DE),
- .HL(HL)
+ .HL(HL),
+ .A_cpu(A_cpu),
+ .Di_cpu(Di_cpu),
+ .Do_cpu(Do_cpu)
);
// Internal ROMs and RAMs
reg [7:0] tetris_rom [0:32767];
initial begin
- $readmemh("data/tetris.rom", tetris_rom, 0, 32768);
+ $readmemh("data/tetris.rom", tetris_rom, 0, 32767);
end
wire [7:0] Di_wram;
@@ -250,9 +266,9 @@ module s6atlys(
.mosi(JB[1]),
.miso(JB[2]),
.sclk(JB[3]),
- .A(A),
- .Di(Di),
- .Do(Do),
+ .A(A_cpu),
+ .Di(Di_cpu),
+ .Do(Do_cpu),
.PC(PC),
.SP(SP),
.AF(AF),
@@ -272,15 +288,27 @@ module s6atlys(
clock_1khz <= !clock_1khz;
if (pulse_200khz)
clock_200khz <= !clock_200khz;
+
if (mode0_sync)
mode <= 2'b00;
- if (mode1_sync)
+ else if (mode1_sync)
mode <= 2'b01;
- if (mode2_sync)
+ else if (mode2_sync)
mode <= 2'b10;
end
end
+ always @(posedge clock) begin
+ if (reset_init) begin
+ clock_divider <= 1'b0;
+ end else begin
+ if (step_enable)
+ clock_divider <= clock_divider + 4;
+ else
+ clock_divider <= clock_divider + 1;
+ end
+ end
+
endmodule
////////////////////////////////////////////////////////////////////////////////
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