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some changes to make it compile

notably the video controller has been completely removed from the implementation and will require significant work to get it working again.
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trun committed Apr 29, 2012
1 parent 3e2cd55 commit c403e48a4e96f28af32c6f4770601b98e25e4eaa
Showing with 79 additions and 53 deletions.
  1. +33 −12 gameboy.v
  2. +3 −4 interrupt_controller.v
  3. +9 −3 memory_controller.v
  4. +10 −10 s6atlys.ucf
  5. +11 −11 s6atlys.v
  6. +11 −12 timer_controller.v
  7. +2 −1 video_controller.v
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@@ -47,19 +47,19 @@ module gameboy (
//assign rd_n = 1'b1;
//assign cs_n = 1'b1;
- assign A_video = 16'b0;
- assign Do_video = 16'b0;
- assign wr_video_n = 1'b1;
- assign rd_video_n = 1'b1;
- assign cs_video_n = 1'b1;
+ //assign A_video = 16'b0;
+ //assign Do_video = 16'b0;
+ //assign wr_video_n = 1'b1;
+ //assign rd_video_n = 1'b1;
+ //assign cs_video_n = 1'b1;
- assign pixel_data = 2'b0;
+ //assign pixel_data = 2'b0;
assign pixel_clock = 1'b0;
- assign pixel_latch = 1'b0;
- assign hsync = 1'b0;
- assign vsync = 1'b0;
+ //assign pixel_latch = 1'b0;
+ //assign hsync = 1'b0;
+ //assign vsync = 1'b0;
- assign joypad_sel = 2'b0;
+ //assign joypad_sel = 2'b0;
assign audio_left = 1'b0;
assign audio_right = 1'b0;
@@ -249,6 +249,7 @@ module gameboy (
// Video Controller
//
+ /*
video_controller video (
.reset(reset),
.clock(clock),
@@ -265,8 +266,28 @@ module gameboy (
.hsync(hsync),
.vsync(vsync),
.pixel_data(pixel_data),
- .pixel_latch(pixel_latch),
- .pixel_clock(clock) // TODO ??
+ .pixel_latch(pixel_latch)
+ //.pixel_clock(clock) // TODO ??
+ );
+ */
+
+ //
+ // Input Controller
+ //
+
+ input_controller joypad_controller (
+ .reset(reset),
+ .clock(clock),
+ .int_ack(int_ack[4]),
+ .int_req(int_req[4]),
+ .A(A),
+ .Di(Do_cpu),
+ .Do(Do_joypad),
+ .cs(cs_timer),
+ .rd_n(rd_n),
+ .wr_n(wr_n),
+ .button_sel(joypad_sel),
+ .button_data(joypad_data)
);
//
View
@@ -39,7 +39,7 @@ module interrupt_controller (
// 1 <= enable
//////////////////////////////////////
- reg[7:0] IF;
+ wire[7:0] IF;
reg[7:0] IE;
parameter POLL_STATE = 0;
@@ -140,10 +140,9 @@ module interrupt_controller (
endcase
end
-
- assign IF = int_req; // this makes the value read only
-
end
+
+ assign IF = int_req; // this makes the value read only
assign Do = (cs) ? reg_out : 8'hFF;
assign int_n = (state == WAIT_STATE) ? 1'b0 : 1'b1; // active low
View
@@ -60,11 +60,17 @@ module memory_controller(
initial begin
$readmemh("data/boot.rom", boot_rom, 0, 255);
- $readmemh("data/jump.rom", jump_rom, 0, 126);
+ $readmemh("data/jump.rom", jump_rom, 0, 9);
end
- // TODO: replace with async ram
- high_ram hr(A_high_ram, Di_cpu, clock, cs_high_ram && !wr_n, Do_high_ram);
+ async_mem #(.asz(8), .depth(127)) high_ram (
+ .rd_data(Do_high_ram),
+ .wr_clk(clock),
+ .wr_data(Di_cpu),
+ .wr_cs(cs_high_ram && ! wr_n),
+ .addr(A_high_ram),
+ .rd_cs(cs_high_ram)
+ );
always @ (posedge clock)
begin
View
@@ -157,16 +157,16 @@
# NET "DDR2RZM" LOC="L6"; # Bank = 3, Pin name = IO_L31P, Sch name = DDR-ODT
# onboard HDMI OUT
- NET "HDMIOUTCLKP" LOC = "B6"; # Bank = 0, Pin name = IO_L8P, Sch name = TMDS-TX-CLK_P
- NET "HDMIOUTCLKN" LOC = "A6"; # Bank = 0, Pin name = IO_L8N_VREF, Sch name = TMDS-TX-CLK_N
- NET "HDMIOUTD0P" LOC = "D8"; # Bank = 0, Pin name = IO_L11P, Sch name = TMDS-TX-0_P
- NET "HDMIOUTD0N" LOC = "C8"; # Bank = 0, Pin name = IO_L11N, Sch name = TMDS-TX-0_N
- NET "HDMIOUTD1P" LOC = "C7"; # Bank = 0, Pin name = IO_L10P, Sch name = TMDS-TX-1_P
- NET "HDMIOUTD1N" LOC = "A7"; # Bank = 0, Pin name = IO_L10N, Sch name = TMDS-TX-1_N
- NET "HDMIOUTD2P" LOC = "B8"; # Bank = 0, Pin name = IO_L33P, Sch name = TMDS-TX-2_P
- NET "HDMIOUTD2N" LOC = "A8"; # Bank = 0, Pin name = IO_L33N, Sch name = TMDS-TX-2_N
- NET "HDMIOUTSCL" LOC = "D9"; # Bank = 0, Pin name = IO_L34P_GCLK19, Sch name = TMDS-TX-SCL
- NET "HDMIOUTSDA" LOC = "C9"; # Bank = 0, Pin name = IO_L34N_GCLK18, Sch name = TMDS-TX-SDA
+# NET "HDMIOUTCLKP" LOC = "B6"; # Bank = 0, Pin name = IO_L8P, Sch name = TMDS-TX-CLK_P
+# NET "HDMIOUTCLKN" LOC = "A6"; # Bank = 0, Pin name = IO_L8N_VREF, Sch name = TMDS-TX-CLK_N
+# NET "HDMIOUTD0P" LOC = "D8"; # Bank = 0, Pin name = IO_L11P, Sch name = TMDS-TX-0_P
+# NET "HDMIOUTD0N" LOC = "C8"; # Bank = 0, Pin name = IO_L11N, Sch name = TMDS-TX-0_N
+# NET "HDMIOUTD1P" LOC = "C7"; # Bank = 0, Pin name = IO_L10P, Sch name = TMDS-TX-1_P
+# NET "HDMIOUTD1N" LOC = "A7"; # Bank = 0, Pin name = IO_L10N, Sch name = TMDS-TX-1_N
+# NET "HDMIOUTD2P" LOC = "B8"; # Bank = 0, Pin name = IO_L33P, Sch name = TMDS-TX-2_P
+# NET "HDMIOUTD2N" LOC = "A8"; # Bank = 0, Pin name = IO_L33N, Sch name = TMDS-TX-2_N
+# NET "HDMIOUTSCL" LOC = "D9"; # Bank = 0, Pin name = IO_L34P_GCLK19, Sch name = TMDS-TX-SCL
+# NET "HDMIOUTSDA" LOC = "C9"; # Bank = 0, Pin name = IO_L34N_GCLK18, Sch name = TMDS-TX-SDA
# onboard HDMI IN1 (PMODA)
# NET "HDMIIN1CLKP" LOC = "D11"; # Bank = 0, Pin name = IO_L36P_GCLK15, Sch name = TMDS-RXB-CLK_P
View
@@ -7,16 +7,16 @@ module s6atlys(
input wire CLK_100M,
// onboard HDMI OUT
- output wire HDMIOUTCLKP,
- output wire HDMIOUTCLKN,
- output wire HDMIOUTD0P,
- output wire HDMIOUTD0N,
- output wire HDMIOUTD1P,
- output wire HDMIOUTD1N,
- output wire HDMIOUTD2P,
- output wire HDMIOUTD2N,
- output wire HDMIOUTSCL,
- output wire HDMIOUTSDA,
+ //output wire HDMIOUTCLKP,
+ //output wire HDMIOUTCLKN,
+ //output wire HDMIOUTD0P,
+ //output wire HDMIOUTD0N,
+ //output wire HDMIOUTD1P,
+ //output wire HDMIOUTD1N,
+ //output wire HDMIOUTD2P,
+ //output wire HDMIOUTD2N,
+ //output wire HDMIOUTSCL,
+ //output wire HDMIOUTSDA,
// LEDs
output wire [7:0] LED,
@@ -25,7 +25,7 @@ module s6atlys(
input wire [7:0] SW,
// Buttons
- input wire [4:0] BTN
+ input wire [5:0] BTN
);
//
View
@@ -8,7 +8,7 @@ module timer_controller (
output reg int_req,
input wire [15:0] A,
input wire [7:0] Di,
- output reg [7:0] Do,
+ output wire [7:0] Do,
input wire wr_n,
input wire rd_n,
input wire cs
@@ -43,7 +43,7 @@ module timer_controller (
parameter MAX_TIMER = 8'hFF;
- reg enable;
+ wire enable;
wire e0, e1, e2, e3;
divider #(1024) d0(reset, clock, e0);
@@ -106,15 +106,14 @@ module timer_controller (
end
end
-
- assign Do = (cs) ? reg_out : 8'hZZ;
- assign enable =
- (TAC[2] == 0) ? 1'b0 :
- (TAC[1:0] == 0) ? e0 :
- (TAC[1:0] == 1) ? e1 :
- (TAC[1:0] == 2) ? e2 :
- (TAC[1:0] == 3) ? e3 : 1'b0;
-
- end
+ end
+
+ assign Do = (cs) ? reg_out : 8'hZZ;
+ assign enable =
+ (TAC[2] == 0) ? 1'b0 :
+ (TAC[1:0] == 0) ? e0 :
+ (TAC[1:0] == 1) ? e1 :
+ (TAC[1:0] == 2) ? e2 :
+ (TAC[1:0] == 3) ? e3 : 1'b0;
endmodule
View
@@ -394,7 +394,8 @@ module video_controller (
assign A_vram = A;
assign Do_vram = Di_video;
- assign A_oam = A;
+ assign A_oam = A;
+ assign Do_oam = 8'b0; // tmp
assign Do =
(cs_vram) ? Do_vram :

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