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cleanup whitespace

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commit df7a8cc93d611b71466d3128c77a3dbaffa3cc6b 1 parent f3b6ce4
@trun authored
Showing with 2 additions and 2 deletions.
  1. +2 −2 divider.v
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4 divider.v
@@ -6,8 +6,8 @@ module divider #(parameter DELAY=50000000) (
input wire clock,
output wire enable);
- reg[31:0] count;
- wire[31:0] next_count;
+ reg [31:0] count;
+ wire [31:0] next_count;
always @(posedge clock)
begin
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