Permalink
Browse files

fix ambiguous naming of pins connecting the PPU <-> MMU and PPU <-> VRAM

  • Loading branch information...
1 parent 0ec106d commit ec60b389d96550a3958949cecd8d9862c9a81829 @trun committed Apr 30, 2012
Showing with 119 additions and 95 deletions.
  1. +55 −30 gameboy.v
  2. +30 −29 memory_controller.v
  3. +12 −11 s6atlys.v
  4. +22 −25 video_controller.v
View
@@ -15,12 +15,12 @@ module gameboy (
output wire cs_n,
// Video RAM
- output wire [15:0] A_video,
- input wire [7:0] Di_video,
- output wire [7:0] Do_video,
- output wire wr_video_n,
- output wire rd_video_n,
- output wire cs_video_n,
+ output wire [15:0] A_vram,
+ input wire [7:0] Di_vram,
+ output wire [7:0] Do_vram,
+ output wire wr_vram_n,
+ output wire rd_vram_n,
+ output wire cs_vram_n,
// Video Display
output wire [1:0] pixel_data,
@@ -155,52 +155,61 @@ module gameboy (
// MMU
//
- wire cs_main;
wire cs_interrupt;
wire cs_timer;
wire cs_video;
wire cs_sound;
wire cs_joypad;
- wire[7:0] Do_mmu;
- wire[7:0] Do_interrupt;
- wire[7:0] Do_timer;
- wire[7:0] Do_sound;
- wire[7:0] Do_joypad;
+ wire [7:0] Do_mmu;
+ wire [7:0] Do_interrupt;
+ wire [7:0] Do_timer;
+ wire [7:0] Do_sound;
+ wire [7:0] Do_joypad;
+
+ wire [15:0] A_ppu;
+ wire [7:0] Do_ppu;
+ wire [7:0] Di_ppu;
+ wire cs_ppu;
memory_controller memory (
.clock(clock),
.reset(reset),
+
+ // CPU <-> MMU
.A_cpu(A_cpu),
.Di_cpu(Do_cpu),
.Do_cpu(Do_mmu),
.rd_cpu_n(rd_cpu_n),
.wr_cpu_n(wr_cpu_n),
+
+ // MMU <-> I/O Registers + External RAMs
.A(A),
.Do(Do),
.Di(Di),
.wr_n(wr_n),
.rd_n(rd_n),
- .cs(cs_main),
- .A_video(A_video),
- .Do_video(Do_video),
- .Di_video(Di_video),
- .rd_video_n(rd_video_n),
- .wr_video_n(wr_video_n),
- .cs_video(cs_video),
+ .cs_n(cs_n),
+
+ // MMU <-> PPU
+ .A_ppu(A_ppu),
+ .Do_ppu(Do_ppu),
+ .Di_ppu(Di_ppu),
+ .cs_ppu(cs_ppu),
+
+ // Data lines (I/O Registers) -> MMU
.Do_interrupt(Do_interrupt),
.Do_timer(Do_timer),
.Do_sound(Do_sound),
.Do_joypad(Do_joypad),
+
+ // MMU -> Modules (I/O Registers)
.cs_interrupt(cs_interrupt),
.cs_timer(cs_timer),
.cs_sound(cs_sound),
.cs_joypad(cs_joypad)
);
- assign cs_n = !cs_main;
- assign cs_video_n = !cs_video;
-
//
// Interrupt Controller
//
@@ -226,6 +235,10 @@ module gameboy (
.Do(Do_interrupt)
);
+ // During an interrupts the CPU reads the jump address
+ // from a table in memory. It gets the address of this
+ // table from the interrupt module which is why this
+ // mux exists.
assign Di_cpu = (!iorq_n && !m1_n) ? jump_addr : Do_mmu;
//
@@ -249,27 +262,39 @@ module gameboy (
// Video Controller
//
- /*
video_controller video (
.reset(reset),
.clock(clock),
+
+ // Interrupts
.int_vblank_ack(int_ack[0]),
.int_vblank_req(int_req[0]),
.int_lcdc_ack(int_ack[1]),
.int_lcdc_req(int_req[1]),
- .A(A_video),
- .Di(Do_video),
- .Do(Di_video),
- .rd_n(rd_video_n),
- .wr_n(wr_video_n),
- .cs(cs_video),
+
+ // PPU <-> MMU
+ .A(A_ppu),
+ .Di(Do_ppu),
+ .Do(Di_ppu),
+ .rd_n(rd_n),
+ .wr_n(wr_n),
+ .cs(cs_ppu),
+
+ // PPU <-> VRAM
+ .A_vram(A_vram),
+ .Di_vram(Do_vram),
+ .Do_vram(Di_vram),
+ .rd_vram_n(rd_vram_n),
+ .wr_vram_n(wr_vram_n),
+ .cs_vram_n(cs_vram_n),
+
+ // LCD Output
.hsync(hsync),
.vsync(vsync),
.pixel_data(pixel_data),
.pixel_latch(pixel_latch)
//.pixel_clock(clock) // TODO ??
);
- */
//
// Input Controller
View
@@ -12,23 +12,23 @@ module memory_controller(
input wire rd_cpu_n,
input wire wr_cpu_n,
- // Main RAM
+ // Main RAM (Cartridge + WRAM)
output wire [15:0] A,
output wire [7:0] Do,
input wire [7:0] Di,
output wire wr_n,
output wire rd_n,
- output wire cs,
+ output wire cs_n,
- // Video RAM
- output wire [15:0] A_video,
- output wire [7:0] Do_video,
- input wire [7:0] Di_video,
- output wire rd_video_n,
- output wire wr_video_n,
- output wire cs_video,
+ // PPU (VRAM + OAM + Registers)
+ output wire [15:0] A_ppu,
+ output wire [7:0] Do_ppu,
+ input wire [7:0] Di_ppu,
+ output wire rd_ppu_n,
+ output wire wr_ppu_n,
+ output wire cs_ppu,
- // Registers
+ // I/O Registers (except for PPU)
input wire [7:0] Do_interrupt,
input wire [7:0] Do_timer,
input wire [7:0] Do_sound,
@@ -51,10 +51,10 @@ module memory_controller(
wire [6:0] A_jump_rom;
wire [6:0] A_high_ram;
- // when 8'h01 gets written into $FF50 the ROM is disabled
- reg rom_enable;
+ // when 8'h01 gets written into FF50h the ROM is disabled
+ reg boot_rom_enable;
- // ROMs
+ // Internal ROMs
reg [7:0] boot_rom [0:255];
reg [7:0] jump_rom [0:9];
@@ -63,11 +63,12 @@ module memory_controller(
$readmemh("data/jump.rom", jump_rom, 0, 9);
end
+ // High RAM
async_mem #(.asz(8), .depth(127)) high_ram (
.rd_data(Do_high_ram),
.wr_clk(clock),
.wr_data(Di_cpu),
- .wr_cs(cs_high_ram && ! wr_n),
+ .wr_cs(cs_high_ram && !wr_n),
.addr(A_high_ram),
.rd_cs(cs_high_ram)
);
@@ -76,7 +77,7 @@ module memory_controller(
begin
if (reset)
begin
- rom_enable <= 1;
+ boot_rom_enable <= 1;
end
else
begin
@@ -87,21 +88,21 @@ module memory_controller(
begin
// TODO: DMA
end
- 16'hFF50: if (Di == 8'h01) rom_enable <= 1'b0;
+ 16'hFF50: if (Di == 8'h01) boot_rom_enable <= 1'b0;
endcase
end
end
end
// selector flags
- assign cs = A < 16'hFE00; // echo of internal ram
+ assign cs_n = (A < 16'hFE00) ? 1'b0 : 1'b1; // echo of internal ram
- assign cs_video =
- (A >= 16'h8000 && A < 16'hA000) || // vram
- (A >= 16'hFE00 && A < 16'hFEA0) || // oam
+ assign cs_ppu =
+ (A >= 16'h8000 && A < 16'hA000) || // VRAM
+ (A >= 16'hFE00 && A < 16'hFEA0) || // OAM
(A >= 16'hFF40 && A <= 16'hFF4B && A != 16'hFF46); // registers (except for DMA)
- assign cs_boot_rom = rom_enable && A < 16'h0100;
+ assign cs_boot_rom = boot_rom_enable && A < 16'h0100;
assign cs_jump_rom = A >= 16'hFEA0 && A < 16'hFF00;
assign cs_high_ram = A >= 16'hFF80 && A < 16'hFFFF;
@@ -110,7 +111,7 @@ module memory_controller(
assign cs_timer = A >= 16'hFF04 && A <= 16'hFF07;
assign cs_joypad = A == 16'hFF00;
- // remap addresses
+ // remap internal addresses
assign A_jump_rom = A - 16'hFEA0;
assign A_high_ram = A - 16'hFF80;
@@ -120,11 +121,11 @@ module memory_controller(
assign wr_n = wr_cpu_n;
assign rd_n = rd_cpu_n;
- // video memory address
- assign A_video = A_cpu;
- assign Do_video = Di_cpu;
- assign wr_video_n = wr_cpu_n;
- assign rd_video_n = rd_cpu_n;
+ // PPU
+ assign A_ppu = A_cpu;
+ assign Do_ppu = Di_cpu;
+ assign wr_ppu_n = wr_cpu_n;
+ assign rd_ppu_n = rd_cpu_n;
assign Do_cpu =
(cs_boot_rom) ? boot_rom[A_cpu] :
@@ -134,7 +135,7 @@ module memory_controller(
(cs_timer) ? Do_timer :
(cs_sound) ? Do_sound :
(cs_joypad) ? Do_joypad :
- (cs_video) ? Do_video :
- (cs) ? Di : 8'hFF;
+ (cs_ppu) ? Do_ppu :
+ (!cs_n) ? Di : 8'hFF;
endmodule
View
@@ -102,10 +102,10 @@ module s6atlys(
wire [7:0] Do;
wire wr_n, rd_n, cs_n;
- wire [15:0] A_video;
- wire [7:0] Di_video;
- wire [7:0] Do_video;
- wire wr_video_n, rd_video_n, cs_video_n;
+ wire [15:0] A_vram;
+ wire [7:0] Di_vram;
+ wire [7:0] Do_vram;
+ wire wr_vram_n, rd_vram_n, cs_vram_n;
wire [1:0] pixel_data;
wire pixel_clock;
@@ -127,12 +127,12 @@ module s6atlys(
.wr_n(wr_n),
.rd_n(rd_n),
.cs_n(cs_n),
- .A_video(A_video),
- .Di_video(Di_video),
- .Do_video(Do_video),
- .wr_video_n(wr_video_n),
- .rd_video_n(rd_video_n),
- .cs_video_n(cs_video_n),
+ .A_vram(A_vram),
+ .Di_vram(Di_vram),
+ .Do_vram(Do_vram),
+ .wr_vram_n(wr_vram_n),
+ .rd_vram_n(rd_vram_n),
+ .cs_vram_n(cs_vram_n),
.pixel_data(pixel_data),
.pixel_clock(pixel_clock),
.pixel_latch(pixel_latch),
@@ -170,8 +170,9 @@ module s6atlys(
end
end
+ // TODO: tie these to 8kb RAMs
assign Di = 8'b0;
- assign Di_video = 8'b0;
+ assign Di_vram = 8'b0;
endmodule
Oops, something went wrong.

0 comments on commit ec60b38

Please sign in to comment.