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fix ambiguous naming of pins connecting the PPU <-> MMU and PPU <-> VRAM

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commit ec60b389d96550a3958949cecd8d9862c9a81829 1 parent 0ec106d
Trevor Rundell authored
85  gameboy.v
@@ -15,12 +15,12 @@ module gameboy (
15 15
   output wire        cs_n,
16 16
   
17 17
   // Video RAM
18  
-  output wire [15:0] A_video,
19  
-  input  wire  [7:0] Di_video,
20  
-  output wire  [7:0] Do_video,
21  
-  output wire        wr_video_n,
22  
-  output wire        rd_video_n,
23  
-  output wire        cs_video_n,
  18
+  output wire [15:0] A_vram,
  19
+  input  wire  [7:0] Di_vram,
  20
+  output wire  [7:0] Do_vram,
  21
+  output wire        wr_vram_n,
  22
+  output wire        rd_vram_n,
  23
+  output wire        cs_vram_n,
24 24
   
25 25
   // Video Display
26 26
   output wire  [1:0] pixel_data,
@@ -155,52 +155,61 @@ module gameboy (
155 155
   // MMU
156 156
   //
157 157
   
158  
-  wire cs_main;
159 158
   wire cs_interrupt;
160 159
   wire cs_timer;
161 160
   wire cs_video;
162 161
   wire cs_sound;
163 162
   wire cs_joypad;
164 163
   
165  
-  wire[7:0] Do_mmu;
166  
-  wire[7:0] Do_interrupt;
167  
-  wire[7:0] Do_timer;
168  
-  wire[7:0] Do_sound;
169  
-  wire[7:0] Do_joypad;
  164
+  wire  [7:0] Do_mmu;
  165
+  wire  [7:0] Do_interrupt;
  166
+  wire  [7:0] Do_timer;
  167
+  wire  [7:0] Do_sound;
  168
+  wire  [7:0] Do_joypad;
  169
+  
  170
+  wire [15:0] A_ppu;
  171
+  wire  [7:0] Do_ppu;
  172
+  wire  [7:0] Di_ppu;
  173
+  wire        cs_ppu;
170 174
   
171 175
   memory_controller memory (
172 176
     .clock(clock),
173 177
     .reset(reset),
  178
+    
  179
+    // CPU <-> MMU
174 180
     .A_cpu(A_cpu),
175 181
     .Di_cpu(Do_cpu),
176 182
     .Do_cpu(Do_mmu),
177 183
     .rd_cpu_n(rd_cpu_n),
178 184
     .wr_cpu_n(wr_cpu_n),
  185
+    
  186
+    // MMU <-> I/O Registers + External RAMs
179 187
     .A(A),
180 188
     .Do(Do),
181 189
     .Di(Di),
182 190
     .wr_n(wr_n),
183 191
     .rd_n(rd_n),
184  
-    .cs(cs_main),
185  
-    .A_video(A_video),
186  
-    .Do_video(Do_video),
187  
-    .Di_video(Di_video),
188  
-    .rd_video_n(rd_video_n),
189  
-    .wr_video_n(wr_video_n),
190  
-    .cs_video(cs_video),
  192
+    .cs_n(cs_n),
  193
+    
  194
+    // MMU <-> PPU
  195
+    .A_ppu(A_ppu),
  196
+    .Do_ppu(Do_ppu),
  197
+    .Di_ppu(Di_ppu),
  198
+    .cs_ppu(cs_ppu),
  199
+    
  200
+    // Data lines (I/O Registers) -> MMU
191 201
     .Do_interrupt(Do_interrupt),
192 202
     .Do_timer(Do_timer),
193 203
     .Do_sound(Do_sound),
194 204
     .Do_joypad(Do_joypad),
  205
+    
  206
+    // MMU -> Modules (I/O Registers)
195 207
     .cs_interrupt(cs_interrupt),
196 208
     .cs_timer(cs_timer),
197 209
     .cs_sound(cs_sound),
198 210
     .cs_joypad(cs_joypad)
199 211
   );
200 212
   
201  
-  assign cs_n = !cs_main;
202  
-  assign cs_video_n = !cs_video;
203  
-  
204 213
   //
205 214
   // Interrupt Controller
206 215
   //
@@ -226,6 +235,10 @@ module gameboy (
226 235
     .Do(Do_interrupt)
227 236
   );
228 237
   
  238
+  // During an interrupts the CPU reads the jump address
  239
+  //  from a table in memory. It gets the address of this
  240
+  //  table from the interrupt module which is why this
  241
+  //  mux exists.
229 242
   assign Di_cpu = (!iorq_n && !m1_n) ? jump_addr : Do_mmu;
230 243
   
231 244
   //
@@ -249,27 +262,39 @@ module gameboy (
249 262
   // Video Controller
250 263
   //
251 264
   
252  
-  /*
253 265
   video_controller video (
254 266
     .reset(reset),
255 267
     .clock(clock),
  268
+    
  269
+    // Interrupts
256 270
     .int_vblank_ack(int_ack[0]),
257 271
     .int_vblank_req(int_req[0]),
258 272
     .int_lcdc_ack(int_ack[1]),
259 273
     .int_lcdc_req(int_req[1]),
260  
-    .A(A_video),
261  
-    .Di(Do_video),
262  
-    .Do(Di_video),
263  
-    .rd_n(rd_video_n),
264  
-    .wr_n(wr_video_n),
265  
-    .cs(cs_video),
  274
+    
  275
+    // PPU <-> MMU
  276
+    .A(A_ppu),
  277
+    .Di(Do_ppu),
  278
+    .Do(Di_ppu),
  279
+    .rd_n(rd_n),
  280
+    .wr_n(wr_n),
  281
+    .cs(cs_ppu),
  282
+    
  283
+    // PPU <-> VRAM
  284
+    .A_vram(A_vram),
  285
+    .Di_vram(Do_vram),
  286
+    .Do_vram(Di_vram),
  287
+    .rd_vram_n(rd_vram_n),
  288
+    .wr_vram_n(wr_vram_n),
  289
+    .cs_vram_n(cs_vram_n),
  290
+    
  291
+    // LCD Output
266 292
     .hsync(hsync),
267 293
     .vsync(vsync),
268 294
     .pixel_data(pixel_data),
269 295
     .pixel_latch(pixel_latch)
270 296
     //.pixel_clock(clock) // TODO ??
271 297
   );
272  
-  */
273 298
   
274 299
   //
275 300
   // Input Controller
59  memory_controller.v
@@ -12,23 +12,23 @@ module memory_controller(
12 12
   input  wire        rd_cpu_n,
13 13
   input  wire        wr_cpu_n,
14 14
   
15  
-  // Main RAM
  15
+  // Main RAM (Cartridge + WRAM)
16 16
   output wire [15:0] A,
17 17
   output wire  [7:0] Do,
18 18
   input  wire  [7:0] Di,
19 19
   output wire        wr_n,
20 20
   output wire        rd_n,
21  
-  output wire        cs,
  21
+  output wire        cs_n,
22 22
   
23  
-  // Video RAM
24  
-  output wire [15:0] A_video,
25  
-  output wire  [7:0] Do_video,
26  
-  input  wire  [7:0] Di_video,
27  
-  output wire        rd_video_n,
28  
-  output wire        wr_video_n,
29  
-  output wire        cs_video,
  23
+  // PPU (VRAM + OAM + Registers)
  24
+  output wire [15:0] A_ppu,
  25
+  output wire  [7:0] Do_ppu,
  26
+  input  wire  [7:0] Di_ppu,
  27
+  output wire        rd_ppu_n,
  28
+  output wire        wr_ppu_n,
  29
+  output wire        cs_ppu,
30 30
   
31  
-  // Registers
  31
+  // I/O Registers (except for PPU)
32 32
   input  wire  [7:0] Do_interrupt,
33 33
   input  wire  [7:0] Do_timer,
34 34
   input  wire  [7:0] Do_sound,
@@ -51,10 +51,10 @@ module memory_controller(
51 51
   wire [6:0] A_jump_rom;
52 52
   wire [6:0] A_high_ram;
53 53
   
54  
-  // when 8'h01 gets written into $FF50 the ROM is disabled
55  
-  reg rom_enable;
  54
+  // when 8'h01 gets written into FF50h the ROM is disabled
  55
+  reg boot_rom_enable;
56 56
   
57  
-  // ROMs
  57
+  // Internal ROMs
58 58
   reg [7:0] boot_rom [0:255];
59 59
   reg [7:0] jump_rom [0:9];
60 60
   
@@ -63,11 +63,12 @@ module memory_controller(
63 63
     $readmemh("data/jump.rom", jump_rom, 0, 9);
64 64
   end
65 65
   
  66
+  // High RAM
66 67
   async_mem #(.asz(8), .depth(127)) high_ram (
67 68
     .rd_data(Do_high_ram),
68 69
     .wr_clk(clock),
69 70
     .wr_data(Di_cpu),
70  
-    .wr_cs(cs_high_ram && ! wr_n),
  71
+    .wr_cs(cs_high_ram && !wr_n),
71 72
     .addr(A_high_ram),
72 73
     .rd_cs(cs_high_ram)
73 74
   );
@@ -76,7 +77,7 @@ module memory_controller(
76 77
   begin
77 78
     if (reset)
78 79
     begin
79  
-      rom_enable <= 1;
  80
+      boot_rom_enable <= 1;
80 81
     end
81 82
     else
82 83
     begin
@@ -87,21 +88,21 @@ module memory_controller(
87 88
           begin
88 89
             // TODO: DMA
89 90
           end
90  
-          16'hFF50: if (Di == 8'h01) rom_enable <= 1'b0;
  91
+          16'hFF50: if (Di == 8'h01) boot_rom_enable <= 1'b0;
91 92
         endcase
92 93
       end
93 94
     end
94 95
   end
95 96
   
96 97
   // selector flags
97  
-  assign cs = A < 16'hFE00; // echo of internal ram
  98
+  assign cs_n = (A < 16'hFE00) ? 1'b0 : 1'b1; // echo of internal ram
98 99
     
99  
-  assign cs_video = 
100  
-    (A >= 16'h8000 && A < 16'hA000) || // vram
101  
-    (A >= 16'hFE00 && A < 16'hFEA0) || // oam
  100
+  assign cs_ppu = 
  101
+    (A >= 16'h8000 && A < 16'hA000) || // VRAM
  102
+    (A >= 16'hFE00 && A < 16'hFEA0) || // OAM
102 103
     (A >= 16'hFF40 && A <= 16'hFF4B && A != 16'hFF46); // registers (except for DMA)
103 104
     
104  
-  assign cs_boot_rom = rom_enable && A < 16'h0100;
  105
+  assign cs_boot_rom = boot_rom_enable && A < 16'h0100;
105 106
   assign cs_jump_rom = A >= 16'hFEA0 && A < 16'hFF00;
106 107
   assign cs_high_ram = A >= 16'hFF80 && A < 16'hFFFF;
107 108
   
@@ -110,7 +111,7 @@ module memory_controller(
110 111
   assign cs_timer = A >= 16'hFF04 && A <= 16'hFF07;
111 112
   assign cs_joypad = A == 16'hFF00;
112 113
   
113  
-  // remap addresses
  114
+  // remap internal addresses
114 115
   assign A_jump_rom = A - 16'hFEA0;
115 116
   assign A_high_ram = A - 16'hFF80;
116 117
   
@@ -120,11 +121,11 @@ module memory_controller(
120 121
   assign wr_n = wr_cpu_n;
121 122
   assign rd_n = rd_cpu_n;
122 123
   
123  
-  // video memory address
124  
-  assign A_video = A_cpu;
125  
-  assign Do_video = Di_cpu;
126  
-  assign wr_video_n = wr_cpu_n;
127  
-  assign rd_video_n = rd_cpu_n;
  124
+  // PPU
  125
+  assign A_ppu = A_cpu;
  126
+  assign Do_ppu = Di_cpu;
  127
+  assign wr_ppu_n = wr_cpu_n;
  128
+  assign rd_ppu_n = rd_cpu_n;
128 129
   
129 130
   assign Do_cpu =
130 131
     (cs_boot_rom) ? boot_rom[A_cpu] :
@@ -134,7 +135,7 @@ module memory_controller(
134 135
     (cs_timer) ? Do_timer :
135 136
     (cs_sound) ? Do_sound :
136 137
     (cs_joypad) ? Do_joypad :
137  
-    (cs_video) ? Do_video :
138  
-    (cs) ? Di : 8'hFF;
  138
+    (cs_ppu) ? Do_ppu :
  139
+    (!cs_n) ? Di : 8'hFF;
139 140
   
140 141
 endmodule
23  s6atlys.v
@@ -102,10 +102,10 @@ module s6atlys(
102 102
   wire [7:0] Do;
103 103
   wire wr_n, rd_n, cs_n;
104 104
   
105  
-  wire [15:0] A_video;
106  
-  wire [7:0] Di_video;
107  
-  wire [7:0] Do_video;
108  
-  wire wr_video_n, rd_video_n, cs_video_n;
  105
+  wire [15:0] A_vram;
  106
+  wire [7:0] Di_vram;
  107
+  wire [7:0] Do_vram;
  108
+  wire wr_vram_n, rd_vram_n, cs_vram_n;
109 109
   
110 110
   wire [1:0] pixel_data;
111 111
   wire pixel_clock;
@@ -127,12 +127,12 @@ module s6atlys(
127 127
     .wr_n(wr_n),
128 128
     .rd_n(rd_n),
129 129
     .cs_n(cs_n),
130  
-    .A_video(A_video),
131  
-    .Di_video(Di_video),
132  
-    .Do_video(Do_video),
133  
-    .wr_video_n(wr_video_n),
134  
-    .rd_video_n(rd_video_n),
135  
-    .cs_video_n(cs_video_n),
  130
+    .A_vram(A_vram),
  131
+    .Di_vram(Di_vram),
  132
+    .Do_vram(Do_vram),
  133
+    .wr_vram_n(wr_vram_n),
  134
+    .rd_vram_n(rd_vram_n),
  135
+    .cs_vram_n(cs_vram_n),
136 136
     .pixel_data(pixel_data),
137 137
     .pixel_clock(pixel_clock),
138 138
     .pixel_latch(pixel_latch),
@@ -170,8 +170,9 @@ module s6atlys(
170 170
     end
171 171
   end
172 172
   
  173
+  // TODO: tie these to 8kb RAMs
173 174
   assign Di = 8'b0;
174  
-  assign Di_video = 8'b0;
  175
+  assign Di_vram = 8'b0;
175 176
   
176 177
 endmodule
177 178
   
47  video_controller.v
@@ -3,29 +3,31 @@
3 3
 
4 4
 module video_controller (
5 5
   input  wire        reset,
6  
-  input  wire        clock,
  6
+  input  wire        clock,
  7
+  
  8
+  // Interrupts
7 9
   input  wire        int_vblank_ack,
8 10
   output reg         int_vblank_req,
9 11
   input  wire        int_lcdc_ack,
10 12
   output reg         int_lcdc_req,
11 13
   
12  
-  // VRAM + OAM + Registers
  14
+  // VRAM + OAM + Registers (PPU <-> MMU)
13 15
   input  wire [15:0] A,
14  
-  input  wire  [7:0] Di,
15  
-  output wire  [7:0] Do,
  16
+  input  wire  [7:0] Di, // in from MMU
  17
+  output wire  [7:0] Do, // out to MMU
16 18
   input  wire        rd_n,
17 19
   input  wire        wr_n,
18 20
   input  wire        cs,
19 21
   
20  
-  // VRAM
21  
-  output wire [15:0] A_video,
22  
-  output wire  [7:0] Do_video, // out to VRAM
23  
-  input  wire  [7:0] Di_video, // in from VRAM
24  
-  output wire        rd_video_n,
25  
-  output wire        wr_video_n,
26  
-  output wire        cs_video,
  22
+  // VRAM (PPU <-> VRAM)
  23
+  output wire [15:0] A_vram,
  24
+  output wire  [7:0] Do_vram, // out to VRAM
  25
+  input  wire  [7:0] Di_vram, // in from VRAM
  26
+  output wire        rd_vram_n,
  27
+  output wire        wr_vram_n,
  28
+  output wire        cs_vram_n,
27 29
   
28  
-  // video output -- TODO pixel clock?
  30
+  // LCD Output -- TODO pixel clock?
29 31
   output wire        hsync,
30 32
   output wire        vsync,
31 33
   output reg   [7:0] line_count,
@@ -200,11 +202,6 @@ module video_controller (
200 202
   wire  [7:0] next_line_count;
201 203
   wire  [8:0] next_pixel_count;
202 204
   
203  
-  wire [12:0] A_vram;
204  
-  wire  [7:0] Do_vram;
205  
-  wire        wr_vram_n;
206  
-  wire        cs_vram;
207  
-  
208 205
   wire  [7:0] A_oam;
209 206
   wire  [7:0] Do_oam;
210 207
   wire        wr_oam_n;
@@ -380,9 +377,9 @@ module video_controller (
380 377
   assign hsync = (pixel_count > OAM_ACTIVE + RAM_ACTIVE + HACTIVE_VIDEO) ? 1'b1 : 1'b0;
381 378
   assign vsync = (line_count > VACTIVE_VIDEO) ? 1'b1 : 1'b0;
382 379
   
383  
-  assign cs_vram = cs && (A >= 16'h8000 && A < 16'hA000);
384  
-  assign cs_oam = cs && (A >= 16'hFE00 && A < 16'hFEA0);
385  
-  assign cs_reg = cs && !cs_vram && !cs_oam;
  380
+  assign cs_vram_n = !(cs && A >= 16'h8000 && A < 16'hA000);
  381
+  assign cs_oam = cs && A >= 16'hFE00 && A < 16'hFEA0;
  382
+  assign cs_reg = cs && cs_vram_n && !cs_oam;
386 383
   
387 384
   assign wr_vram_n = !(cs_oam && !wr_n && mode != RAM_LOCK_MODE);
388 385
   assign wr_oam_n = !(cs_oam && !wr_n && mode != RAM_LOCK_MODE && mode != OAM_LOCK_MODE);
@@ -391,14 +388,14 @@ module video_controller (
391 388
   assign STAT[2] = (line_count == LYC) ? 1 : 0; // LYC Coincidence flag
392 389
   assign STAT[1:0] = mode; // read only -- set internally
393 390
   
394  
-  assign A_vram = A;
395  
-  assign Do_vram = Di_video;
  391
+  assign A_vram = A; // TODO: mux
  392
+  assign Do_vram = Di; // TODO: mux
396 393
   
397  
-  assign A_oam = A;
398  
-  assign Do_oam = 8'b0; // tmp
  394
+  assign A_oam = A; // TODO: offset and mux
  395
+  assign Do_oam = 8'b0; // TODO: Di and mux
399 396
   
400 397
   assign Do =
401  
-    (cs_vram) ? Do_vram :
  398
+    (!cs_vram_n) ? Do_vram :
402 399
     (cs_oam) ? Do_oam :
403 400
     (cs_reg) ? Do_reg : 8'hFF;
404 401
 

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