diff --git a/lib/components/normal-components/Board.ts b/lib/components/normal-components/Board.ts
index 1979f6699..a06ace615 100644
--- a/lib/components/normal-components/Board.ts
+++ b/lib/components/normal-components/Board.ts
@@ -118,8 +118,8 @@ export class Board extends Group<typeof boardProps> {
     const { db } = this.root!
     const { _parsedProps: props } = this
 
-    // Skip if width and height are explicitly provided
-    if (props.width && props.height) return
+    // Skip if width and height are explicitly provided or if outline is provided
+    if ((props.width && props.height) || props.outline) return
 
     let minX = Infinity
     let minY = Infinity
@@ -182,7 +182,7 @@ export class Board extends Group<typeof boardProps> {
     const computedHeight = hasComponents ? maxY - minY + padding * 2 : 0
 
     // Center the board around the components or use (0,0) for empty boards
-    let center = {
+    const center = {
       x: hasComponents
         ? (minX + maxX) / 2 + (props.outlineOffsetX ?? 0)
         : (props.outlineOffsetX ?? 0),
@@ -195,7 +195,7 @@ export class Board extends Group<typeof boardProps> {
     const finalWidth = props.width ?? computedWidth
     const finalHeight = props.height ?? computedHeight
 
-    let outline = props.outline
+    let outline = props.outline as { x: number; y: number }[] | undefined
     if (
       !outline &&
       props.borderRadius != null &&
diff --git a/tests/components/normal-components/__snapshots__/board-outline-dimension-pcb.snap.svg b/tests/components/normal-components/__snapshots__/board-outline-dimension-pcb.snap.svg
new file mode 100644
index 000000000..1b14f178c
--- /dev/null
+++ b/tests/components/normal-components/__snapshots__/board-outline-dimension-pcb.snap.svg
@@ -0,0 +1 @@
+<svg xmlns="http://www.w3.org/2000/svg" width="800" height="600" data-software-used-string="@tscircuit/core@0.0.793"><style></style><rect class="boundary" x="0" y="0" fill="#000" width="800" height="600" data-type="pcb_background" data-pcb-layer="global"/><rect class="pcb-boundary" fill="none" stroke="#fff" stroke-width="0.3" x="133.33333333333331" y="33.333333333333314" width="533.3333333333335" height="533.3333333333335" data-type="pcb_boundary" data-pcb-layer="global"/><path class="pcb-board" d="M 133.33333333333331 566.6666666666667 L 666.6666666666667 566.6666666666667 L 666.6666666666667 33.333333333333314 L 133.33333333333331 33.333333333333314 Z" fill="none" stroke="rgba(255, 255, 255, 0.5)" stroke-width="3.333333333333334" data-type="pcb_board" data-pcb-layer="board"/><rect class="pcb-pad" fill="rgb(200, 52, 52)" x="374" y="289.3333333333333" width="18.000000000000004" height="21.333333333333336" data-type="pcb_smtpad" data-pcb-layer="top"/><rect class="pcb-pad" fill="rgb(200, 52, 52)" x="408" y="289.3333333333333" width="18.000000000000004" height="21.333333333333336" data-type="pcb_smtpad" data-pcb-layer="top"/><rect class="pcb-pad" fill="rgb(200, 52, 52)" x="359.1666666666667" y="344.00000000000006" width="26.66666666666667" height="31.666666666666668" data-type="pcb_smtpad" data-pcb-layer="top"/><rect class="pcb-pad" fill="rgb(200, 52, 52)" x="414.1666666666667" y="344.00000000000006" width="26.66666666666667" height="31.666666666666668" data-type="pcb_smtpad" data-pcb-layer="top"/><path class="pcb-silkscreen pcb-silkscreen-top" d="M 417 276 L 367.3333333333333 276 L 367.3333333333333 324 L 417 324" fill="none" stroke="#f2eda1" stroke-width="3.333333333333334" stroke-linecap="round" stroke-linejoin="round" data-pcb-component-id="pcb_component_0" data-pcb-silkscreen-path-id="pcb_silkscreen_path_0" data-type="pcb_silkscreen_path" data-pcb-layer="top"/><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="13.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,400,259.3333333333333)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">R1</text><path class="pcb-silkscreen pcb-silkscreen-top" d="M 427.5 330.6666666666667 L 352.5 330.6666666666667 L 352.5 389 L 427.5 389" fill="none" stroke="#f2eda1" stroke-width="3.333333333333334" stroke-linecap="round" stroke-linejoin="round" data-pcb-component-id="pcb_component_1" data-pcb-silkscreen-path-id="pcb_silkscreen_path_1" data-type="pcb_silkscreen_path" data-pcb-layer="top"/><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="13.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,400,405.6666666666667)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_1" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">C1</text></svg>
\ No newline at end of file
diff --git a/tests/components/normal-components/board-outline-dimension.test.tsx b/tests/components/normal-components/board-outline-dimension.test.tsx
new file mode 100644
index 000000000..91e14b818
--- /dev/null
+++ b/tests/components/normal-components/board-outline-dimension.test.tsx
@@ -0,0 +1,28 @@
+import { test, expect } from "bun:test"
+import { getTestFixture } from "tests/fixtures/get-test-fixture"
+
+test("board outline dimension is calculated correctly", () => {
+  const { circuit } = getTestFixture()
+
+  circuit.add(
+    <board
+      outline={[
+        { x: -8, y: -8 },
+        { x: 8, y: -8 },
+        { x: 8, y: 8 },
+        { x: -8, y: 8 },
+      ]}
+    >
+      <resistor name="R1" resistance="10k" footprint="0402" />
+      <capacitor name="C1" capacitance="10uF" footprint="0603" />
+    </board>,
+  )
+
+  circuit.render()
+
+  const pcb_board = circuit.db.pcb_board.list()[0]
+  expect(pcb_board.width).toBe(16)
+  expect(pcb_board.height).toBe(16)
+
+  expect(circuit).toMatchPcbSnapshot(import.meta.path)
+})