From b2f7c10dd10a43a109f598b3535e679934b7711e Mon Sep 17 00:00:00 2001 From: Dasdebsankar54 Date: Sun, 16 Nov 2025 10:59:44 +0530 Subject: [PATCH 1/2] WIP --- .../createSchematicTraceSolverInputProblem.ts | 107 ++++++++++++++---- 1 file changed, 85 insertions(+), 22 deletions(-) diff --git a/lib/components/primitive-components/Group/Group_doInitialSchematicTraceRender/createSchematicTraceSolverInputProblem.ts b/lib/components/primitive-components/Group/Group_doInitialSchematicTraceRender/createSchematicTraceSolverInputProblem.ts index d115bac4e..1e8fc8610 100644 --- a/lib/components/primitive-components/Group/Group_doInitialSchematicTraceRender/createSchematicTraceSolverInputProblem.ts +++ b/lib/components/primitive-components/Group/Group_doInitialSchematicTraceRender/createSchematicTraceSolverInputProblem.ts @@ -174,6 +174,9 @@ export function createSchematicTraceSolverInputProblem( const directConnections: Array<{ pinIds: [string, string]; netId?: string }> = [] const pairKeyToSourceTraceId = new Map() + // This set is used to decouple net label orientation from net connections + const allInScopeNetNames = new Set() + for (const st of db.source_trace.list()) { if (st.subcircuit_id && !allowedSubcircuitIds.has(st.subcircuit_id)) { continue @@ -197,6 +200,9 @@ export function createSchematicTraceSolverInputProblem( userNetIdToSck.set(userNetId, st.subcircuit_connectivity_map_key) sckToUserNetId.set(st.subcircuit_connectivity_map_key, userNetId) } + if (userNetId) { + allInScopeNetNames.add(userNetId); + } directConnections.push({ pinIds: [a, b].map((id) => schematicPortIdToPinId.get(id)!) as [ string, @@ -241,27 +247,81 @@ export function createSchematicTraceSolverInputProblem( for (const [subcircuitConnectivityKey, schematicPortIds] of sckToPinIds) { const sourceNet = sckToSourceNet.get(subcircuitConnectivityKey) if (sourceNet && schematicPortIds.length >= 2) { - const userNetId = String( - sourceNet.name || sourceNet.source_net_id || subcircuitConnectivityKey, - ) + const hasExplicitTrace = db.source_trace + .list() + .some( + (st) => + st.subcircuit_connectivity_map_key === subcircuitConnectivityKey + ); + + const userLabeledThisNet = Boolean( + sourceNet?.name && sourceNet.name.trim() !== "" + ); + + if (sourceNet.name) { + allInScopeNetNames.add(sourceNet.name); + } + + // Only create a netConnection if: + // 1. There's exactly 2 ports (simple case: netlabel connects two specific components) + // 2. OR there's an explicit trace connecting them (user explicitly routed this net) + // + // Skip if there are 3+ ports without an explicit trace, as this indicates + // multiple separate netlabel instances targeting different components + // (which should NOT be auto-connected together). + if (sourceNet && schematicPortIds.length === 2 && userLabeledThisNet) { + // This is the "net jumping" fix: + // If it's a ground or power net (AND there is NO explicit trace), + // skip making the connection. + if (sourceNet.is_ground || sourceNet.is_power) { + continue; + } + + const userNetId = String( + sourceNet.name || sourceNet.source_net_id || subcircuitConnectivityKey, + ) userNetIdToSck.set(userNetId, subcircuitConnectivityKey) sckToUserNetId.set(subcircuitConnectivityKey, userNetId) - // Estimate net label width using same heuristic as computeSchematicNetLabelCenter - // Default font_size is 0.18 and charWidth = 0.1 * (font_size / 0.18) - const fontSize = 0.18 - const charWidth = 0.1 * (fontSize / 0.18) - const netLabelWidth = Number( - (String(userNetId).length * charWidth).toFixed(2), - ) + // Estimate net label width using same heuristic as computeSchematicNetLabelCenter + // Default font_size is 0.18 and charWidth = 0.1 * (font_size / 0.18) + const fontSize = 0.18 + const charWidth = 0.1 * (fontSize / 0.18) + const netLabelWidth = Number( + (String(userNetId).length * charWidth).toFixed(2), + ) - netConnections.push({ - netId: userNetId, - pinIds: schematicPortIds.map( - (portId) => schematicPortIdToPinId.get(portId)!, - ), - netLabelWidth, - }) + netConnections.push({ + netId: userNetId, + pinIds: schematicPortIds.map( + (portId) => schematicPortIdToPinId.get(portId)!, + ), + netLabelWidth, + }) + } else if (hasExplicitTrace && userLabeledThisNet) { + // This is the fix for the 12 failing tests: + // If there's an explicit trace, honor it regardless of pin count + // and ALWAYS create the connection, even for GND/VCC. + const userNetId = String( + sourceNet.name || sourceNet.source_net_id || subcircuitConnectivityKey + ); + userNetIdToSck.set(userNetId, subcircuitConnectivityKey); + sckToUserNetId.set(subcircuitConnectivityKey, userNetId); + + const fontSize = 0.18; + const charWidth = 0.1 * (fontSize / 0.18); + const netLabelWidth = Number( + (String(userNetId).length * charWidth).toFixed(2) + ); + + netConnections.push({ + netId: userNetId, + pinIds: schematicPortIds.map( + (portId) => schematicPortIdToPinId.get(portId)! + ), + netLabelWidth, + }); + } } } @@ -269,17 +329,20 @@ export function createSchematicTraceSolverInputProblem( const availableNetLabelOrientations: Record = (() => { const netToAllowedOrientations: Record = {} - const presentNetIds = new Set(netConnections.map((nc) => nc.netId)) + // Use allInScopeNetNames so that labels for GND/VCC get oriented + // even if we skipped their connection. for (const net of db.source_net .list() .filter( (n) => !n.subcircuit_id || allowedSubcircuitIds.has(n.subcircuit_id), )) { - if (!net.name) continue - if (!presentNetIds.has(net.name)) continue - if (net.is_ground || net.name.toLowerCase().startsWith("gnd")) { + if (!net.name) continue; + if (!allInScopeNetNames.has(net.name)) continue + + // FIXED: Removed hard-coded string checks + if (net.is_ground) { netToAllowedOrientations[net.name] = ["y-"] - } else if (net.is_power || net.name.toLowerCase().startsWith("v")) { + } else if (net.is_power) { netToAllowedOrientations[net.name] = ["y+"] } else { netToAllowedOrientations[net.name] = ["x-", "x+"] From 2db933d118a24490089a9fbc48d5f72867fd7f9e Mon Sep 17 00:00:00 2001 From: Dasdebsankar54 Date: Sun, 16 Nov 2025 11:06:18 +0530 Subject: [PATCH 2/2] WIP --- .../rotated-components-schematic.snap.svg | 35 +++++- ...ulator-with-connections-schematic.snap.svg | 111 ++++++++++++------ .../group-match-adapt3-schematic.snap.svg | 71 ++++++----- ...e-regulator-match-adapt-schematic.snap.svg | 16 +-- ...arging-voltage-divider-simulation.snap.svg | 40 ++++--- ...ge-divider-custom-time-simulation.snap.svg | 40 ++++--- .../repro23-trace-overlap-schematic.snap.svg | 15 ++- ...5-pinheader-connections-schematic.snap.svg | 64 ++++++---- .../repro46-automatic-sch-schematic.snap.svg | 16 ++- ...erlap-junction-crossing-schematic.snap.svg | 59 ++++++---- ...matic-trace-net-jumping-schematic.snap.svg | 9 +- ...ate-source-drain-access-schematic.snap.svg | 28 ++--- 12 files changed, 309 insertions(+), 195 deletions(-) diff --git a/tests/components/normal-components/__snapshots__/rotated-components-schematic.snap.svg b/tests/components/normal-components/__snapshots__/rotated-components-schematic.snap.svg index 660426d6f..b0ddeacc2 100644 --- a/tests/components/normal-components/__snapshots__/rotated-components-schematic.snap.svg +++ b/tests/components/normal-components/__snapshots__/rotated-components-schematic.snap.svg @@ -1,4 +1,4 @@ --1,-2-1,-1-1,0-1,1-1,20,-20,-10,00,10,21,-21,-11,01,11,22,-22,-12,02,12,23,-23,-13,03,13,24,-24,-14,04,14,25,-25,-15,05,15,26,-26,-16,06,16,27,-27,-17,07,17,28,-28,-18,08,18,29,-29,-19,09,19,210,-210,-110,010,110,211,-211,-111,011,111,212,-212,-112,012,112,2R110kΩL1I110kHC110kD1D2VCCGNDVCCGND \ No newline at end of file diff --git a/tests/examples/__snapshots__/example7-voltage-regulator-with-connections-schematic.snap.svg b/tests/examples/__snapshots__/example7-voltage-regulator-with-connections-schematic.snap.svg index 84ea54319..ed2293ca0 100644 --- a/tests/examples/__snapshots__/example7-voltage-regulator-with-connections-schematic.snap.svg +++ b/tests/examples/__snapshots__/example7-voltage-regulator-with-connections-schematic.snap.svg @@ -1,4 +1,4 @@ - \ No newline at end of file diff --git a/tests/features/schematic-match-adapt/__snapshots__/group-match-adapt3-schematic.snap.svg b/tests/features/schematic-match-adapt/__snapshots__/group-match-adapt3-schematic.snap.svg index 67db009d7..cbdad25c6 100644 --- a/tests/features/schematic-match-adapt/__snapshots__/group-match-adapt3-schematic.snap.svg +++ b/tests/features/schematic-match-adapt/__snapshots__/group-match-adapt3-schematic.snap.svg @@ -1,4 +1,4 @@ - \ No newline at end of file diff --git a/tests/features/schematic-match-adapt/__snapshots__/voltage-regulator-match-adapt-schematic.snap.svg b/tests/features/schematic-match-adapt/__snapshots__/voltage-regulator-match-adapt-schematic.snap.svg index b6c44ca8f..5a8cf8f96 100644 --- a/tests/features/schematic-match-adapt/__snapshots__/voltage-regulator-match-adapt-schematic.snap.svg +++ b/tests/features/schematic-match-adapt/__snapshots__/voltage-regulator-match-adapt-schematic.snap.svg @@ -1,4 +1,4 @@ --6,-2-6,-1-6,0-6,1-6,2-6,3-5,-2-5,-1-5,0-5,1-5,2-5,3-4,-2-4,-1-4,0-4,1-4,2-4,3-3,-2-3,-1-3,0-3,1-3,2-3,3-2,-2-2,-1-2,0-2,1-2,2-2,3-1,-2-1,-1-1,0-1,1-1,2-1,30,-20,-10,00,10,20,31,-21,-11,01,11,21,32,-22,-12,02,12,22,3C62.2uFC12.2uFC22.2uFC51uFRT9013_33GBU11VIN2GND3EN4NC5VOUTVSYSGNDGNDV3_3 \ No newline at end of file diff --git a/tests/features/spice-analysis/__snapshots__/spice-analysis03-rc-charging-voltage-divider-simulation.snap.svg b/tests/features/spice-analysis/__snapshots__/spice-analysis03-rc-charging-voltage-divider-simulation.snap.svg index 6b9c9ff04..8d2dc93af 100644 --- a/tests/features/spice-analysis/__snapshots__/spice-analysis03-rc-charging-voltage-divider-simulation.snap.svg +++ b/tests/features/spice-analysis/__snapshots__/spice-analysis03-rc-charging-voltage-divider-simulation.snap.svg @@ -1,4 +1,4 @@ -