diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index ad0f8565d374..3d214f2479ed 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -27,7 +27,7 @@
 		};
                 service_reserved1: svcbuffer@1 {
                         compatible = "shared-dma-pool";
-                        reg = <0x0 0x7F000000 0x0 0x7FFFFFFF>;
+                        reg = <0x0 0x56A00000 0x0 0x20000000>;
                         alignment = <0x1000>;
                         no-map;
                 };
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts
index 7071a0e229e2..92307404588e 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts
@@ -181,14 +181,8 @@
 	};
 };
 
-/* To test TXE blob with DDR, we need to comment out PCIE & SSD */
-#ifdef DDR_ACCESS
 &pcie_0_pcie_aglx {
 	status = "okay";
 	compatible = "altr,pcie-root-port-3.0-f-tile";
-	/* interrupts = <0 0 0>; */
-/*	interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
-	interupt_parent = <&intc>; */
 };
-#endif