From 23af72f0b3224787861aacb95c3bef41c4d2e35e Mon Sep 17 00:00:00 2001 From: Ashish Trivedi Date: Tue, 15 Oct 2024 15:15:30 -0700 Subject: [PATCH 1/2] @FIR-214: Added 512 MB Reserved memory pool for Model This change adds a 512 MB contiguous memory area for model data Moved the reserved area from 0x7f100000 to 0x56A00000 and fixed the size to 512MB --- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index ad0f8565d374..3d214f2479ed 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -27,7 +27,7 @@ }; service_reserved1: svcbuffer@1 { compatible = "shared-dma-pool"; - reg = <0x0 0x7F000000 0x0 0x7FFFFFFF>; + reg = <0x0 0x56A00000 0x0 0x20000000>; alignment = <0x1000>; no-map; }; From d2b9b6fb4a1707fe845f71fbfa71769c98cf7b02 Mon Sep 17 00:00:00 2001 From: Ashish Trivedi Date: Wed, 16 Oct 2024 12:43:49 -0700 Subject: [PATCH 2/2] @FIR-214: Enabling the PCI-E for NVME Added back to PCI-E config This change has been validated in a combined image of NVME and DDR based command queue --- arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts index 7071a0e229e2..92307404588e 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts @@ -181,14 +181,8 @@ }; }; -/* To test TXE blob with DDR, we need to comment out PCIE & SSD */ -#ifdef DDR_ACCESS &pcie_0_pcie_aglx { status = "okay"; compatible = "altr,pcie-root-port-3.0-f-tile"; - /* interrupts = <0 0 0>; */ -/* interrupts = <32 IRQ_TYPE_LEVEL_HIGH>; - interupt_parent = <&intc>; */ }; -#endif