# tsung-wei-huang/ECE462

The class repository for ECE462 - Logic Synthesis
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# Welcome to Logic Synthesis (ECE462) at UIUC!

This course teaches you how to extract gate-level circuits from high-level description languages and apply top-down design methodology to optimize the designs to achieve better power, performance, timing, and area.

# Class Logistics

• Instructor: Dr. Tsung-Wei Huang
• TA: Linz Chiang
• Email: ylc2 at illinois dot edu
• Time: 11:00 AM - 12:15 PM every Tue/Thr (excluding holidays)
• Room: 3081 ECE Building
• Webpage: https://github.com/twhuang-uiuc/ECE462
• Scoring (130 points):
• Midterm 1: 20 points (2/21 - 2/26)
• Midterm 2: 20 points
• Final: 30 points (see here)
• Homework: 50 points
• Class participation: 10 points
• Office hour:
• Tsung-Wei Huang: 11-12 PM every Friday at CSL 402 (or by appointment)
• Linz Chiang: 10:00 AM - 11:00 AM every Saturday and Sunday at ECEB 3034 (unless otherwise noted)
• Last day of office hour is Apr. 28, SUN.
• Text book (OPTIONAL):
• Hachtel and Somenzi, Logic Synthesis and Verification Algorithms.

• Last four digits of UIN is listed with grades.
• Attendence and Quiz (Date column)
• Yes means attended = 1 pt
• No means absence = 0 pt
• 0 means wrong answer = 0 pt
• 0.5 means partially right answer = 0.5 pt
• 1 means right answer = 1 pt
• Out of 100 pts
• 0 means no submission = 0 pt

## Quiz Notes

### Quiz 1

• 0.5 points for K-map and 4-variable logic function
• 0.5 points for Quine-McCluskey methods
• If one step is wrong, you lose the point.

### Quiz 2

• 1 point for correct answer: (z'+a+b)(z+a'+b)(z+a+b')(z'+a'+b')
• 0.5 partial credits for logic function: z XNOR (a XOR b)

# Syllabus

The class will teach you the following topics:

• Digital circuit design flow
• Fundamental boolean algebra
• Karnaugh maps and Quine-McCluskey method
• Binary decision diagrams (BDD)
• Finite state machines
• Equivalence checking
• Multi-level logic synthesis
• Timing analysis, physical design, and verification
• Other advanced topics and new research trends

# Lecture Notes

Lecture Topics Slides Homework Due
Lecture 1 (2019/1/15) Introduction to Logic Synthesis (I) lecture1.pdf - -
Lecture 2 (2019/1/17) Introduction to Logic Synthesis (II) lecture2.pdf - -
Lecture 3 (2019/1/22) Boolean Algebra (I) lecture3.pdf - -
Lecture 4 (2019/1/24) Boolean Algebra (II) see above - -
Lecture 5 (2019/1/29) K-Map lecture5.pdf Homework 1 2/12 in class
Lecture 6 (2019/1/31) Quine-McCluskey Method lecture6.pdf - -
No class (2019/2/05) - - - -
Lecture 7 (2019/2/07) Binary Decision Diagram (I) lecture7.pdf - -
Lecture 8 (2019/2/12) Binary Decision Diagram (II) lecture8.pdf - HW1 Solution
Lecture 9 (2019/2/14) Satisfiability (I) lecture9.pdf Homework 2 HW2 Solution
Midterm (2019/2/21) Midterm 1 - Midterm 1 MT1 Solution
Lecture 10 (2019/2/26) Satisfiability (II) lecture10.pdf - -
Lecture 11 (2019/2/28) Introduction to MiniSat lecture11.pdf Homework 3 HW3 Solution
Lecture 12 (2019/3/05) Two-level Logic Synthesis (I) lecture12.pdf - -
Lecture 13 (2019/3/07) Two-level Logic Synthesis (II) lecture13.pdf - -
Lecture 14 (2019/3/12) Multilevel Logic Synthesis (I) lecture14.pdf - -
Lecture 15 (2019/3/14) Introduction to Espresso lecture15.pdf Homework 4 HW4 Solution
Lecture 16 (2019/3/25) Multilevel Logic Synthesis (II) lecture16.pdf - -
Lecture 17 (2019/3/27) Multilevel Logic Synthesis (III) lecture17.pdf - -
Midterm (2019/4/02) Midterm 2 - Midterm 2 MT2 Solution
Lecture 18 (2019/4/4) Multilevel Logic Synthesis (IV) lecture18.pdf - -
Lecture 19 (2019/4/9) Multilevel Logic Synthesis (V) lecture19.pdf - -
Lecture 20 (2019/4/11) DC extraction lecture20.pdf Homework 5 -
Lecture 21 (2019/4/16) Technology Mapping (I) lecture21.pdf - -
Lecture 22 (2019/4/18) Technology Mapping (II) lecture22.pdf - -

# Homework Directions

• Write your name, your netID, and homework (HW1, HW2, etc.) on the first page.
• Please use full letter/A4 size paper and staple your homework on the top left corner.
• Homework can be either CLEARLY written or typed.
• SHOW YOUR WORK. Points will not be given even if the answer is correct. Partial credits will be given based on your work.
• Failed to do the above will result in point deduction.

## Homework 1

### Clarification

• For question 4.3, use either AND gate or OR gate to implement AB + CD. If you dont think it is possible, simply write down it is not possible with reasoning. If you use both AND gate and OR gate, I will give you partial credits.
• For question 4.4, you can only select one gate either NAND or NOR gate for question 4.4) to implement AB + CD.

### Notes

• Points are NOT negotiable unless I misunderstand your answer or there are other solutions I didn't think of.
• Think about Q1 when you do the homework! The point of logic synthesis is to get the optimized result.
• Verify your answer! Q2 should be very straightforward if you spend 2 minutes to verify the result to be a'c.

## Homework 2

### Clarification

• For question 3, there should be five variables a, b, c, d, e rather than four variables.

## Homewrok 4

### Rubric

• Q1: 15 points
• Q2: 5 points
• Q3: 10 points
• Q4: 55 points
• Q5: 15 points

# Exam Logistics

## Midterm 1

• The exam will be posted HERE at 11:00 PM on Thursday (Feb. 21).
• The midterm 1 solution is available HERE.
• It is due on the following Tuesday (Feb. 26) in class.
• The solution must be either CLEARLY WRITTEN or TYPED, and must be submitted in paper format.
• The exam covers Boolean algebra, k-map, Quine-McCluskey, and BDD.
• You are welcome to use online sources/textbooks/slides and discuss with your fellow classmates.
• You are NOT allowed to ask TA or professor about the exam problems. Neither can you copy from other people's work. Cheating will result in -100 points.

### Statistics

• Mean: 82.90816327
• Median: 83.5
• Standard deviation: 11.51478826

• The regrade request must be submitted during office hour BEFORE Mar. 24.
• Regrade will ONLY be accepted in the following cases:
• The grading is inconsistent with the rubric.

## Midterm 2

• The exam will be posted HERE at 11:00 PM on Tuesday (Apr. 2).
• The midterm 2 solution is available HERE.
• It is due on the Thursday (Apr. 4) in class.
• The solution must be either CLEARLY WRITTEN or TYPED, and must be submitted in paper format.
• The exam covers satisfisbility, 2-level logic synthesis, multi-level logic synthesis, etc.
• You are welcome to use online sources/textbooks/slides and discuss with your fellow classmates.
• You are NOT allowed to ask TA or professor about the exam problems. Neither can you copy from other people's work. Cheating will result in -100 points.
• Late penalty is -30%.

### Statistics

• Mean: 87.75
• Median: 95.5
• Standard deviation: 20.7564

## Final

The university has decided the final exam schedule for ECE462:

• Date: 5/8/19 (Wednesday)
• Time: 8:00 am – 11:00 am
• Room: 1015 ECEB

You can visit the official course explorer to find out more details.

We have very strict academic dishonesty policy. The University will record any violation on your transcript. Please read 1‑402 ACADEMIC INTEGRITY INFRACTIONS carefully to understand the consequence of any violations.

# Acknowledgment

The class staff appreciate many people for sharing their course materials with us to improve the class.

• Shobha Vasudevan, UIUC ECE
• Deming Chen, UIUC ECE
• Yao-Wen Chang, NTU EE
• Hung-Ming Chen, NCTU EE
• Pierre-Emmanuel and Xifan Tan, UT ECE
• Rob Rutenbar, U Pitt

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