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Running a grlib-gpl Leon3 inside my ZestSC1

This repo contains my (unexpectedly) successful creation of a LEON3 inside my ZestSC1 FPGA board. The work was based on the GPL version of Gaisler's GRLIB, and was performed in one week: from the weekend of March 2nd 2019, and all through the four evenings that followed it (after work).

Finally, in the evening of March 7th I proudly saw my board respond to GRMON3:

Video of victory

I also kept a complete log of the attempt as I was going, here.

So... I "compiled" my own CPU! Another "magic thing" demystified :-)

And since I begun learning the ropes 30 years ago on a SPARCstation running at 40MHz... the emotional high of "compiling my own SPARC" in my FPGA was, well, priceless :-)

Hats off to the Gaisler people; for making things so easy that even a complete newbie (HW-wise) like me, can actually put the pieces together.

UPDATE: Here's the complete log of the execution of the Dhrystone 2.1 benchmark in my Leon3; a benchmark that I barely managed to squeeze in my puny 16KB of BlockRAM :-)

Running a grlib-gpl Leon3 inside my Pano Logic G2

UPDATE, many months later: I got my hands on a Pano Logic G2, thanks to the magnificent Tom Verbeure.

After soldering my, erm, custom JTAG "adapter"...

Soldering JTAG...

Soldering other end of JTAG...

...I was able to "see" the board from my Arch Linux:

Natively seeing an LX100 under Arch Linux, with the free WebPACK

...and two evenings later, I bootstrapped a Leon3 again - but this time, via JTAG (order(s) of magnitude faster than UART), and since the XC6LX100 is a monster (compared to the Spartan3), with 16 times more memory, and 4 Leon3 cores!

A Leon3 inside a Pano Logic G2

In any case, I need to write a blog post about this - I've done too many things, that must be documented.

UPDATE: I finally found the willpower to document everything, in a very detailed blog post. Enjoy!


My optimistic - yet unexpectedly successful - attempt to create a LEON3 inside my FPGA boards (ZestSC1, Pano Logic G2)



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