{"payload":{"header_redesign_enabled":false,"results":[{"id":"42392309","archived":false,"color":"#DAE1C2","followers":4,"has_funding_file":true,"hl_name":"tudortimi/prog_assert","hl_trunc_description":"Program assertion package for SystemVerilog","language":"SystemVerilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":42392309,"name":"prog_assert","owner_id":8170909,"owner_login":"tudortimi","updated_at":"2023-01-15T15:52:26.450Z","has_issues":true}},"sponsorable":true,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":55,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Atudortimi%252Fprog_assert%2B%2Blanguage%253ASystemVerilog","metadata":null,"csrf_tokens":{"/tudortimi/prog_assert/star":{"post":"0L0J0VYHwLQzYNmOp7F2F1wZYVn4jPBZPZQyfijih-y07oi6YEVeBrUhvwTO13i6hjwDOGfQzUSyYqV1k7t1vQ"},"/tudortimi/prog_assert/unstar":{"post":"LpaBsRen0aKiS7mnYLjAjJegy0xwsFrKFzpptec75aQJLv8DNh1jt9SU71twRsCBGZMOemmMGIZzlaIJ3KavQQ"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"FQwgiWYfHob_6p9dkYC1c1muOA3mXrNZv0BGHDVQS9RS1o9D0rUXZ2-Yz5kpGiq951no4xhHj0zEkDRZWaRAVw"}}},"title":"Repository search results"}