v5.1

What's Changed

• Added interface calculations for DDR4
• Added multiple device implementations for DDR5, LPDDR4, LPDDR5
• Upgraded DRAMPower CLI tool
• Introduced common SI units
• Based MemSpecs on new internal DRAMUtils library ( https://github.com/tukl-msd/DRAMUtils )

DRAMPower v5.0-RC1

• Complete rewrite of the DRAMPower Simulator
• DRAMPower is now a library, which will be used in DRAMSys
• Interface Power can now be calculated
• Based on CMake build system
• New standards: LPDDR4, LPDDR5, DDR4, DDR5
• Generic and standard-specific tests (also in CI)

DRAMPower v4.1

Small Changes...

New DRAMPower 5.0 will be released soon.

DRAMPower v4.0

Major changes:

• DRAMPower can now be compiled as a library. This enables a user
  to access the tool through an API and log commands and their
  corresponding time stamps, removing the need to store large
  command traces on disk. In addition, cycle counting variables
  have been changed to int64 to support longer simulations.
  The library can be compiled without Xerces to remove an optional
  dependency and reduce the size of the binary.
• Improved robustness. The latest build is automatically checked
  out on a test server, compiled, and tested to verify that the
  output matches an expected reference. The code is also compiled
  with a large number of warning flags enabled and treats all
  warnings as errors.
• Bug fix: Fixed bug in io/termination energy calculation.
• Bug fix: Fixed bug in calculation of auto precharge cycle.

For detailed change information you may browse the commits section.

Version 3.1

Version 3.1 was released on 14th November 2013

• Added IO and Termination Power measures from Micron's DRAM Power
  Calculator, for all supported DRAM generations. In the case of
  Wide IO DRAMs, these measures are already included in the provided
  current specifications. This feature enables support for multi-rank
  DRAM DIMMs (DDR2/3/4) and stacking of multiple Wide IO DRAM dies
  (equivalent to ranks). To indicate use of multi-rank DRAMs or
  multiple Wide IO DRAM dies/layers, the 'nbrOfRanks' parameter in
  the memory specification XMLs can be employed. Note: The DRAM
  command scheduler does not support multi-rank/multi-die DRAMs yet.
  Only the power estimation component of DRAMPower has been updated
  to support them. The current measures for dual-rank DRAMs only
  reflect those for the active rank and not the idle rank. The
  default state of the idle rank is assumed to be the same as the
  current memory state, for background power estimation. Hence,
  rank information in the command trace is not required.
• Added warning messages: New warning messages are provided, to
  identify if the memory or bank state is inconsistent in the
  user-defined traces. Towards this, a state check is performed on
  every memory command issued.
• Improved run-time options: Users can now point directly to the
  memory specification XML, instead of just the memory ID. Also,
  users can optionally include IO and termination power estimates
  (for both single and dual rank DRAMs) using '-r' flag in the
  command line options.
• Bug fixes: (1) Refresh handler in the DRAM Command Scheduler was
  kept ON in the Self-Refresh mode, when it can be turned OFF. This
  bug has now been fixed. (2) Precharge All (PREA) always considered
  precharging of all banks. It has now been modified to consider
  precharging of the open/active banks alone.