# twhuang-uiuc/ECE462

The class repository for ECE462 - Logic Synthesis
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# Welcome to Logic Synthesis (ECE462) at UIUC!

This course teaches you how to extract gate-level circuits from high-level description languages and apply top-down design methodology to optimize the designs to achieve better power, performance, timing, and area.

# Class Logistics

• Instructor: Dr. Tsung-Wei Huang
• TA: Linz Chiang
• Email: ylc2 at illinois dot edu
• Time: 11:00 AM - 12:15 PM every Tue/Thr (excluding holidays)
• Room: 3081 ECE Building
• Webpage: https://github.com/twhuang-uiuc/ECE462
• Scoring (130 points):
• Midterm 1: 20 points
• Midterm 2: 20 points
• Final: 30 points (see here)
• Homework: 50 points
• Class participation: 10 points
• Office hour:
• Tsung-Wei Huang: 11-12 PM every Friday at CSL 402 (or by appointment)
• Linz Chiang: 10:00 AM - 11:00 AM every Saturday and Sunday at ECEB 3034 (unless otherwise noted)
• Text book (OPTIONAL):
• Hachtel and Somenzi, Logic Synthesis and Verification Algorithms.

# Syllabus

The class will teach you the following topics:

• Digital circuit design flow
• Fundamental boolean algebra
• Karnaugh maps and Quine-McCluskey method
• Binary decision diagrams (BDD)
• Finite state machines
• Equivalence checking
• Multi-level logic synthesis
• Timing analysis, physical design, and verification
• Other advanced topics and new research trends
Lecture Topics Slides Homework Due
Lecture 1 (2019/01/15) Introduction to Logic Synthesis (I) lecture1.pdf - -
Lecture 2 (2019/01/17) Introduction to Logic Synthesis (II) lecture2.pdf - -
Lecture 3 (2019/01/22) Boolean Algebra (I) lecture3.pdf - -