-
Notifications
You must be signed in to change notification settings - Fork 3.6k
/
armada-8040-puzzle-m801.dts
383 lines (338 loc) · 6.89 KB
/
armada-8040-puzzle-m801.dts
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2016 Marvell International Ltd.
* Copyright (C) 2020 Sartura Ltd.
*/
#include "armada-8040.dtsi" /* include SoC device tree */
/ {
model = "iEi-Puzzle-M801";
compatible = "marvell,armada8040-puzzle-m801",
"marvell,armada8040";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
i2c0 = &ap_i2c0;
i2c1 = &cp0_i2c0;
i2c2 = &cp0_i2c1;
i2c3 = &i2c_switch;
spi0 = &ap_spi0;
gpio0 = &ap_gpio0;
gpio1 = &cp0_gpio0;
gpio2 = &cp0_gpio1;
gpio3 = &sfpplus_gpio;
};
memory@00000000 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
simple-bus {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb3h0_vbus: usb3-vbus0 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&cp0_xhci_vbus_pins>;
regulator-name = "reg-usb3h0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
startup-delay-us = <500000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&cp0_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */
};
};
};
&ap_i2c0 {
status = "okay";
clock-frequency = <100000>;
rtc@32 {
compatible = "epson,rx8010";
reg = <0x32>;
};
};
&uart0 {
status = "okay";
};
&ap_pinctl {
/*
* MPP Bus:
* AP SPI0 [0-3]
* AP I2C [4-5]
* AP GPIO [6]
* AP UART 1 RX/TX [7-8]
* AP GPIO [9-10]
* AP GPIO [12]
* UART0 [11,19]
*/
/* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 3 3 3 3 3 3 3 3 3 0
0 3 0 0 0 0 0 0 0 3 >;
};
&cp0_pinctl {
/*
* MPP Bus:
* [0-31] = 0xff: Keep default CP0_shared_pins:
* [11] CLKOUT_MPP_11 (out)
* [23] LINK_RD_IN_CP2CP (in)
* [25] CLKOUT_MPP_25 (out)
* [29] AVS_FB_IN_CP2CP (in)
* [32,34] SMI
* [33] MSS power down
* [35-38] CP0 I2C1 and I2C0
* [39] MSS CKE Enable
* [40,41] CP0 UART1 TX/RX
* [42,43] XSMI (controls two 10G phys)
* [47] USB VBUS EN
* [48] FAN PWM
* [49] 10G port 1 interrupt
* [50] 10G port 0 interrupt
* [51] 2.5G SFP TX fault
* [52] PCIe reset out
* [53] 2.5G SFP mode
* [54] 2.5G SFP LOS
* [55] Micro SD card detect
* [56-61] Micro SD
* [62] CP1 SFI SFP FAULT
*/
/* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0 7 0xa 7 2 2 2 2 0xa
7 7 8 8 0 0 0 0 0 0
0 0 0 0 0 0 0xe 0xe 0xe 0xe
0xe 0xe 0 >;
cp0_xhci_vbus_pins: cpm-xhci-vbus-pins {
marvell,pins = < 47 >;
marvell,function = <0>;
};
cp0_pcie_reset_pins: cpm-pcie-reset-pins {
marvell,pins = < 52 >;
marvell,function = <0>;
};
};
&cp0_sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_sdhci_pins>;
bus-width= <4>;
status = "okay";
};
&cp0_pcie0 {
num-lanes = <1>;
pinctrl-names = "default";
pinctrl-0 = <&cp0_pcie_reset_pins>;
marvell,reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */
status = "okay";
};
&cp0_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
sfpplus_gpio: gpio@21 {
compatible = "nxp,pca9555";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
};
&cp0_i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c1_pins>;
status = "okay";
clock-frequency = <100000>;
i2c_switch: i2c-switch@70 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
};
};
&cp0_sata0 {
status = "okay";
};
&cp0_ethernet {
pinctrl-names = "default";
status = "okay";
};
&cp0_mdio {
status = "okay";
cp0_ge_phy0: ethernet-phy@1 {
reg = <0>;
};
cp0_ge_phy1: ethernet-phy@2 {
reg = <1>;
};
};
&cp0_eth0 {
status = "okay";
phy-mode = "sfi";
};
&cp0_eth1 {
status = "okay";
phy-mode = "sgmii";
phy = <&cp0_ge_phy0>;
};
&cp0_eth2 {
status = "okay";
phy-mode = "sgmii";
phy = <&cp0_ge_phy1>;
};
&cp0_comphy {
/*
* CP0 Serdes Configuration:
* Lane 0: PCIe0 (x1)
* Lane 1: SGMII2
* Lane 2: SATA0
* Lane 3: SGMII1
* Lane 4: SFI (10G)
* Lane 5: SATA1
*/
phy0 {
phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
phy-type = <COMPHY_TYPE_SGMII2>;
phy-speed = <COMPHY_SPEED_1_25G>;
};
phy2 {
phy-type = <COMPHY_TYPE_SATA0>;
};
phy3 {
phy-type = <COMPHY_TYPE_SGMII1>;
phy-speed = <COMPHY_SPEED_1_25G>;
};
phy4 {
phy-type = <COMPHY_TYPE_SFI0>;
};
phy5 {
phy-type = <COMPHY_TYPE_SATA1>;
};
};
&cp1_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp1_smi_pins>;
cp1_ge_phy0: ethernet-phy@3 {
reg = <1>;
};
cp1_ge_phy1: ethernet-phy@4 {
reg = <0>;
};
};
&cp1_pcie0 {
num-lanes = <2>;
pinctrl-names = "default";
status = "okay";
};
&cp1_usb3_0 {
vbus-supply = <®_usb3h0_vbus>;
status = "okay";
};
&cp1_utmi0 {
status = "okay";
};
&cp1_ethernet {
status = "okay";
};
&cp1_eth0 {
status = "okay";
phy-mode = "sfi";
};
&cp1_eth1 {
status = "okay";
phy = <&cp1_ge_phy0>;
phy-mode = "sgmii";
};
&cp1_eth2 {
status = "okay";
phy = <&cp1_ge_phy1>;
phy-mode = "sgmii";
};
&cp1_pinctl {
/*
* MPP Bus:
* [0-5] TDM
* [27-28] SMI
* [29-30] CP1 MSS I2C
* [6-26, 31] GPIO
* [32-62] = 0xff: Keep default CP1_shared_pins:
*/
/* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x8 0x8 0x8
0x8 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff>;
cp1_smi_pins: cp1-smi-pins {
marvell,pins = < 27 28 >;
marvell,function = <8>;
};
};
&ap_spi0 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@u-boot {
reg = <0x00000000 0x001f0000>;
label = "u-boot";
};
partition@u-boot-env {
reg = <0x001f0000 0x00010000>;
label = "u-boot-env";
};
partition@ubi1 {
reg = <0x00200000 0x03f00000>;
label = "ubi1";
};
partition@ubi2 {
reg = <0x04100000 0x03f00000>;
label = "ubi2";
};
};
};
};
&cp1_comphy {
/*
* CP1 Serdes Configuration:
* Lane 0: PCIe0 (x2)
* Lane 1: PCIe0 (x2)
* Lane 2: USB HOST 0
* Lane 3: SGMII1
* Lane 4: SFI (10G)
* Lane 5: SGMII2
*/
phy0 {
phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
phy-type = <COMPHY_TYPE_PEX0>;
};
phy2 {
phy-type = <COMPHY_TYPE_USB3_HOST0>;
};
phy3 {
phy-type = <COMPHY_TYPE_SGMII1>;
phy-speed = <COMPHY_SPEED_1_25G>;
};
phy4 {
phy-type = <COMPHY_TYPE_SFI0>;
};
phy5 {
phy-type = <COMPHY_TYPE_SGMII2>;
phy-speed = <COMPHY_SPEED_1_25G>;
};
};