fsl-ls1046a-frwy.dts

// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
 * Device Tree Include file for NXP Layerscape-1046A family SoC.
 *
 * Copyright 2019-2023 NXP
 *
 */

/dts-v1/;
#include "fsl-ls1046a.dtsi"

/ {
	model = "LS1046A FRWY Board";

	aliases {
		spi0 = &qspi;
		serial0 = &duart0;
		serial1 = &duart1;
		serial2 = &duart2;
		serial3 = &duart3;
	};

};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

&duart2 {
	status = "okay";
};

&duart3 {
	status = "okay";
};

&qspi {
	status = "okay";

	mt25qu512a0: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-max-frequency = <50000000>;
		reg = <0>;
	};

};

&i2c0 {
	status = "okay";
};

#include "fsl-ls1046-post.dtsi"

&fman0 {
	ethernet@e0000 {
		phy-handle = <&qsgmii_phy4>;
		phy-connection-type = "qsgmii";
		status = "okay";
	};

	ethernet@e8000 {
		phy-handle = <&qsgmii_phy2>;
		phy-connection-type = "qsgmii";
		status = "okay";
	};

	ethernet@ea000 {
		phy-handle = <&qsgmii_phy1>;
		phy-connection-type = "qsgmii";
		status = "okay";
	};

	ethernet@f2000 {
		phy-handle = <&qsgmii_phy3>;
		phy-connection-type = "qsgmii";
		status = "okay";
	};

	mdio@fd000 {
		qsgmii_phy1: ethernet-phy@1c {
			reg = <0x1c>;
		};

		qsgmii_phy2: ethernet-phy@1d {
			reg = <0x1d>;
		};

		qsgmii_phy3: ethernet-phy@1e {
			reg = <0x1e>;
		};

		qsgmii_phy4: ethernet-phy@1f {
			reg = <0x1f>;
		};
	};
};