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Final code with correct printing format

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u7karsh committed Nov 13, 2017
1 parent be7d19b commit cfb3b3f99f026ba9ddc3eec74cf7f36223261744
Showing with 89 additions and 54 deletions.
  1. +6 −4 Makefile
  2. +6 −2 cache.c
  3. +29 −30 ds.c
  4. +31 −15 ds.h
  5. +0 −3 fifo.h
  6. +17 −0 main.c
@@ -1,23 +1,25 @@
CC = gcc
#OPT = -O3 -m32 --std=c99
OPT = -g
OPT = -O3 -m32 --std=c99
#OPT = -g
WARN = -Wall
CFLAGS = $(OPT) $(WARN) $(INC) $(LIB)

# List all your .cc files here (source files, excluding header files)
SIM_SRC = main.c ds.c fifo.c cache.c
SIM_SRC = $(wildcard *.c)

# List corresponding compiled object files here (.o files)
SIM_OBJ = main.o ds.o fifo.o cache.o
SIM_OBJ = $(SIM_SRC:.c=.o)

#################################

# default rule
.PHONY: all
all: sim
@echo "my work is done here..."


# rule for making sim
.PHONY: sim
sim: $(SIM_OBJ)
$(CC) -o sim $(CFLAGS) $(SIM_OBJ) -lm
@echo "-----------DONE WITH SIM -----------"
@@ -9,6 +9,7 @@
* CHANGES :
* Added Support to multi level cache : UM : 20 Sep 17
* Added Victim cache : UM : 26 Sep 17
* Fixed NULL tray crash : UM : 12 Nov 17
*
*H***********************************************************************/

@@ -555,15 +556,18 @@ void cachePrettyPrintConfig( cachePT cacheP )
void cachePrintContents( cachePT cacheP )
{
if( !cacheP ) return;
printf("===== %s contents =====\n", cacheP->name);
printf("%s CACHE CONTENTS\n", cacheP->name);
printf("a. number of accesses :%d\n", cacheP->readHitCount + cacheP->readMissCount + cacheP->writeHitCount + cacheP->writeMissCount);
printf("b. number of misses :%d\n", cacheP->readMissCount + cacheP->writeMissCount);
for( int setIndex = 0; setIndex < cacheP->nSets; setIndex++ ){
printf("set\t\t%d:\t\t", setIndex);
printf("set %d :", setIndex);
tagPT *rowP = cacheP->tagStoreP[setIndex]->rowP;
for( int assocIndex = 0; assocIndex < cacheP->assoc; assocIndex++ ){
printf("%x %c\t", rowP[assocIndex]->tag, (rowP[assocIndex]->dirty) ? 'D' : ' ' );
}
printf("\n");
}
printf("\n");
}

inline int cacheGetWBCount( cachePT cacheP )
59 ds.c
@@ -12,12 +12,6 @@

#include "ds.h"

// Since this is a small proj, add all utils in this
// file instead of a separate file
//-------------- UTILITY BEGIN -----------------

//-------------- UTILITY END -----------------

// Allocates and inits all internal variables
dsPT dynamicSchedulerInit(
char* name,
@@ -75,20 +69,11 @@ boolean dsProcess( dsPT dsP )
return result;
}

// If instruction is in execute, check if it has executed
boolean dsInstInEx( dsPT dsP, dsInstInfoPT instP )
{
// If instruction is in execute,
// Type 0 takes 0 cycles
// Type 1 takes 2 cycles
// Type 2 takes 5 cycles
if( instP->stage == PROC_PIPE_STAGE_EX ){
if( instP->type == 0 ){
return TRUE;
} else if( instP->type == 1 ){
return ((dsP->cycle - instP->exStart) >= 2) ? TRUE : FALSE;
} else{
return ((dsP->cycle - instP->exStart) >= instP->delay) ? TRUE : FALSE;
}
return ((dsP->cycle - instP->exStart) >= instP->latency) ? TRUE : FALSE;
}
return FALSE;
}
@@ -109,7 +94,6 @@ boolean fakeRetire( dsPT dsP )
dsInstInfoPT infoP = fifoPopTailConditional( dsP->fakeRobP, &success, dsInstInWB );
if( success ){
printf("%d fu{%d} src{%d,%d} dst{%d} IF{%d,%d} ID{%d,%d} IS{%d,%d} EX{%d,%d} WB{%d,%d}\n",
//infoP->sequenceNum, infoP->type, infoP->src1, infoP->src2, infoP->dst,
infoP->sequenceNum, infoP->type, infoP->origSrc1, infoP->origSrc2, infoP->dst,
infoP->ifStart, infoP->ifDuration,
infoP->idStart, infoP->idDuration,
@@ -205,27 +189,36 @@ boolean issue( dsPT dsP )
}
fifoForeach( dsP->issueList, dsIssuer, dsP );

// If execute list is not full
//TODO
int iss = 0;
while( /*fifoNumElems( dsP->executeList )*/ iss < dsP->n && fifoNumElems( dsP->tempQ ) > 0 ){
// FUs are pipelined and can take upto N instructions every cycle
// NOTE: Do not limit executions based on size of executeList as FUs are pipelined
int iss = 0;
while( iss < dsP->n && fifoNumElems( dsP->tempQ ) > 0 ){
dsInstInfoPT instP= fifoPop( dsP->tempQ );
iss++;
instP->isDuration = dsP->cycle - instP->isStart;
instP->exStart = dsP->cycle;
instP->stage = PROC_PIPE_STAGE_EX;

// Memory operation on cache
if( instP->type == 2 ){
cacheCommT comm = cacheCommunicate( dsP->l1P, instP->mem, CMD_DIR_READ );
// NOTE: cacheCommunicate is smart enough to return miss if no cache is present
// ----------------- CACHE PLUGIN BEGIN -------------------
if( instP->type == PROC_INST_TYPE2 && dsP->l1P != NULL ){
cacheCommT comm = cacheCommunicate( dsP->l1P, instP->mem, CMD_DIR_READ );
if( !comm.hit ){
cacheCommT comm = cacheCommunicate( dsP->l2P, instP->mem, CMD_DIR_READ );
// L1 Miss
instP->latency = PIPE_EX_LATENCY_L1MISS;
comm = cacheCommunicate( dsP->l2P, instP->mem, CMD_DIR_READ );
if( !comm.hit ){
instP->delay = 20;
}else{
instP->delay = 10;
// L2 Miss
instP->latency = PIPE_EX_LATENCY_L2MISS;
}
} else{
// L1 Hit
instP->latency = PIPE_EX_LATENCY_L1HIT;
}
}
// ----------------- CACHE PLUGIN END ---------------------

fifoPush( dsP->executeList, instP );
// Remove from dispatch list
fifoSearchOpRemove( dsP->issueList, dsInstSeqNum, NULL, &(instP->sequenceNum), TRUE );
@@ -352,14 +345,20 @@ boolean fetch( dsPT dsP )
instP->src2 = src2;
instP->origSrc1 = src1;
instP->origSrc2 = src2;
instP->delay = 5;
instP->mem = mem;
instP->sequenceNum = dsP->seqNum++;

// Assign execution latency based on operation type
switch( operation ){
case PROC_INST_TYPE0: instP->latency = PIPE_EX_LATENCY_TYPE0; break;
case PROC_INST_TYPE1: instP->latency = PIPE_EX_LATENCY_TYPE1; break;
default : instP->latency = PIPE_EX_LATENCY_TYPE2; break;
}

// Push onto Fake ROB
fifoPush( dsP->fakeRobP, instP );
// Add instruction to dispatchList
fifoPush( dsP->dispatchList, instP );

} else{
return TRUE;
}
46 ds.h
@@ -18,15 +18,22 @@
#include "fifo.h"
#include "cache.h"

// Mask for 32 bit address
#define MSB_ONE_32_BIT 0x80000000
// Execution latencies
#define PIPE_EX_LATENCY_TYPE0 0
#define PIPE_EX_LATENCY_TYPE1 2
#define PIPE_EX_LATENCY_TYPE2 5

// Memory latencies
#define PIPE_EX_LATENCY_L1HIT 5
#define PIPE_EX_LATENCY_L1MISS 10
#define PIPE_EX_LATENCY_L2MISS 20

// Pointer translations
typedef struct _dsT *dsPT;
typedef struct _dsInstInfoT *dsInstInfoPT;
typedef struct _dsCapsuleT *dsCapsulePT;

// Emums
// Emums for pipeline stages
typedef enum{
PROC_PIPE_STAGE_IF = 0,
PROC_PIPE_STAGE_ID = 1,
@@ -35,6 +42,12 @@ typedef enum{
PROC_PIPE_STAGE_WB = 4
}procPipeStageT;

typedef enum{
PROC_INST_TYPE0 = 0,
PROC_INST_TYPE1 = 1,
PROC_INST_TYPE2 = 2
}procInstructionT;

// Dynamic Instruction Scheduler structure.
typedef struct _dsT{
/*
@@ -80,7 +93,7 @@ typedef struct _dsInstInfoT{
int origSrc1;
int origSrc2;
int dst;
int delay;
int latency;
int mem;

int src1Ready; // Src1 ready state
@@ -125,16 +138,19 @@ dsPT dynamicSchedulerInit(
int l2Assoc
);

boolean dsProcess( dsPT dsP );
boolean dsInstInEx( dsPT dsP, dsInstInfoPT instP );
boolean dsInstInWB( dsInstInfoPT instP );
boolean fakeRetire( dsPT dsP );
boolean execute( dsPT dsP );
void dsIssuer( dsPT dsP, dsInstInfoPT instP );
boolean issue( dsPT dsP );
void dsDispatcher( dsPT dsP, dsInstInfoPT instP );
boolean dsInstSeqNum( int* seqNum, dsInstInfoPT instP );
boolean dispatch( dsPT dsP );
boolean fetch( dsPT dsP );
boolean dsProcess( dsPT dsP );
boolean dsInstInEx( dsPT dsP, dsInstInfoPT instP );
boolean dsInstInWB( dsInstInfoPT instP );
boolean fakeRetire( dsPT dsP );
void dsWakeup( int *reg, dsInstInfoPT instP );
void dsSearchDst( int *dstFlag, dsInstInfoPT instP );
void dsExFinish( dsPT dsP, dsInstInfoPT instP );
boolean execute( dsPT dsP );
void dsIssuer( dsPT dsP, dsInstInfoPT instP );
boolean issue( dsPT dsP );
void dsDispatcher( dsPT dsP, dsInstInfoPT instP );
boolean dsInstSeqNum( int* seqNum, dsInstInfoPT instP );
boolean dispatch( dsPT dsP );
boolean fetch( dsPT dsP );

#endif
3 fifo.h
@@ -16,9 +16,6 @@

#include "all.h"

// Mask for 32 bit address
#define MSB_ONE_32_BIT 0x80000000

// Pointer translations
typedef struct _fifoT *fifoPT;
typedef struct _fifoCellT *fifoCellPT;
17 main.c
@@ -13,6 +13,9 @@
#include "all.h"
#include "ds.h"

int numInstructions = 0;

// Trace function to be mapped with init
boolean doTrace( dsPT dsP, int* pcP, int* operationP, int* dstP, int* src1P, int* src2P, int* memP )
{
int pc, operation, dst, src1, src2, mem;
@@ -35,6 +38,7 @@ boolean doTrace( dsPT dsP, int* pcP, int* operationP, int* dstP, int* src1P, int
*src1P = src1;
*src2P = src2;
*memP = mem;
numInstructions++;
return TRUE;
}
return FALSE;
@@ -57,7 +61,20 @@ int main( int argc, char** argv )

dsPT dsP = dynamicSchedulerInit( "DS", fp, s, n, doTrace, blockSize, l1Size, l1Assoc, l2Size, l2Assoc );
while( !dsProcess( dsP ) );

cachePrintContents( dsP->l1P );
cachePrintContents( dsP->l2P );

// Print coniguration of dsP
printf("CONFIGURATION\n");
printf(" superscalar bandwidth (N) = %d\n", dsP->n);
printf(" dispatch queue size (2*N) = %d\n", 2*dsP->n);
printf(" schedule queue size (S) = %d\n", dsP->s);
printf("RESULTS\n");
printf(" number of instructions = %d\n", numInstructions);
// Cycle - 1 as it stands one ahead
int cycles = dsP->cycle - 1;
printf(" number of cycles = %d\n", cycles);
printf(" IPC = %0.2f\n", (double)numInstructions / (double)(cycles));

}

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