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the hard part is done.

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uberj committed Oct 18, 2012
1 parent ae0b396 commit 8ce63e6e45d73b85cc7431291b298c6fa2144b65
Showing with 15 additions and 10 deletions.
  1. +3 −1 labs/proj3/ALU16.v
  2. +7 −4 labs/proj3/alu_slice_msb.v
  3. +5 −5 labs/proj3/mux.v
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@@ -42,6 +42,8 @@ module ALU16(A_i, B_i, Operation_Code_i, zero_o, S_o, overflow_o, carry_o);
alu_slice_1bit alu1b12(A_i[12], B_i[12], S_o[12], c[12], c[13], zero, binvt, Operation_Code_i);
alu_slice_1bit alu1b13(A_i[13], B_i[13], S_o[13], c[13], c[14], zero, binvt, Operation_Code_i);
alu_slice_1bit alu1b14(A_i[14], B_i[14], S_o[14], c[14], c[15], zero, binvt, Operation_Code_i);
- alu_slice_msb alu1b15(A_i[15], B_i[15], S_o[15], c[15], overflow_o, set, binvt, Operation_Code_i);
+ alu_slice_msb msb(A_i[15], B_i[15], S_o[15], c[15], carry_o, overflow_o, set, binvt, Operation_Code_i);
+
+ assign zero_o = (S_o == 0) ? 1 : 0;
endmodule
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@@ -2,23 +2,26 @@
* Kevin Ngo and Jacques Uber
* (1 bit) ALU slice MSB
*/
-module alu_slice_msb(a, b, alu_out, cin, oflo, set, binvt, operation);
+module alu_slice_msb(a, b, alu_out, cin, cout, oflo, set, binvt, operation);
input a, b, cin, binvt, operation;
input [2:0] operation;
output alu_out;
output set;
+ output cout;
output oflo; // Over flow
- wire [3:0] mux_in;
- wire fa_b;
wire cout; // Used to calculate oflo
wire mx_out;
wire zero;
+ wire msb_sum;
+ wire tmp1, tmp2;
assign zero = 0;
alu_slice_1bit inner_alu(a, b, alu_out, cin, cout, zero, binvt, operation);
assign oflo = (cout ^ cin) ? 1: 0;
// The 'Set' output is dependent upon the opcode
// selecting 'set on less than' and the overflow being 1.
- assign set = (operation == 7 & oflo) ? 1: 0;
+ assign fa_b = b ^ binvt;
+ fulladder f0(a, fa_b, cin, msb_sum, tmp1);
+ assign set = (operation == 3'b111 & msb_sum) ? 1: 0;
endmodule
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@@ -12,11 +12,11 @@ module mux(in, sel, out);
always @(in or sel)
begin
case (sel)
- 0: out = in[0];
- 1: out = in[1];
- 2: out = in[2];
- 6: out = in[3];
- 7: out = 0;
+ 3'b000: out = in[0];
+ 3'b001: out = in[1];
+ 3'b010: out = in[2];
+ 3'b110: out = in[2];
+ 3'b111: out = in[3];
endcase
end
endmodule

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