diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index e6671996c7..576c690bc3 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -44,8 +44,8 @@ mapping["chipyard-digitaltop"]=" TOP=DigitalTop" mapping["chipyard-streaming-fir"]=" CONFIG=StreamingFIRRocketConfig" mapping["chipyard-streaming-passthrough"]=" CONFIG=StreamingPassthroughRocketConfig" mapping["chipyard-hetero"]=" CONFIG=LargeBoomAndRocketConfig" -mapping["chipyard-boom"]=" CONFIG=SmallBoomConfig" -mapping["chipyard-spike"]=" CONFIG=SpikeConfig" +mapping["chipyard-boom"]=" CONFIG=MediumBoomCosimConfig" +mapping["chipyard-spike"]=" CONFIG=SpikeFastUARTConfig EXTRA_SIM_FLAGS='+spike-ipc=10'" mapping["chipyard-blkdev"]=" CONFIG=SimBlockDeviceRocketConfig" mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig" mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig" diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index 750f35a231..ccac2b9822 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -320,7 +320,6 @@ jobs: uses: ./.github/actions/prepare-rtl with: group-key: "group-accels" - toolchain: "esp-tools" prepare-chipyard-tracegen: name: prepare-chipyard-tracegen @@ -689,7 +688,6 @@ jobs: with: group-key: "group-accels" project-key: "chipyard-sha3" - toolchain: "esp-tools" chipyard-streaming-fir-run-tests: name: chipyard-streaming-fir-run-tests @@ -737,30 +735,6 @@ jobs: group-key: "group-accels" project-key: "chipyard-streaming-passthrough" - chipyard-hwacha-run-tests: - name: chipyard-hwacha-run-tests - needs: prepare-chipyard-accels - runs-on: self-hosted - steps: - - name: Delete old checkout - run: | - ls -alh . - rm -rf ${{ github.workspace }}/* || true - rm -rf ${{ github.workspace }}/.* || true - ls -alh . - - name: Checkout - uses: actions/checkout@v3 - - name: Git workaround - uses: ./.github/actions/git-workaround - - name: Create conda env - uses: ./.github/actions/create-conda-env - - name: Run tests - uses: ./.github/actions/run-tests - with: - group-key: "group-accels" - project-key: "chipyard-hwacha" - toolchain: "esp-tools" - chipyard-gemmini-run-tests: name: chipyard-gemmini-run-tests needs: prepare-chipyard-accels @@ -783,7 +757,6 @@ jobs: with: group-key: "group-accels" project-key: "chipyard-gemmini" - toolchain: "esp-tools" chipyard-nvdla-run-tests: name: chipyard-nvdla-run-tests @@ -830,7 +803,6 @@ jobs: with: group-key: "group-accels" project-key: "chipyard-mempress" - toolchain: "esp-tools" tracegen-boom-run-tests: @@ -1043,7 +1015,6 @@ jobs: chipyard-sha3-run-tests, chipyard-streaming-fir-run-tests, chipyard-streaming-passthrough-run-tests, - chipyard-hwacha-run-tests, chipyard-gemmini-run-tests, chipyard-nvdla-run-tests, chipyard-mempress-run-tests, diff --git a/generators/chipyard/src/main/resources/csrc/cospike.cc b/generators/chipyard/src/main/resources/csrc/cospike.cc new file mode 100644 index 0000000000..084e1b2877 --- /dev/null +++ b/generators/chipyard/src/main/resources/csrc/cospike.cc @@ -0,0 +1,257 @@ +#include +#include +#include +#include +#include +#include +#include + +#define CLINT_BASE (0x2000000) +#define CLINT_SIZE (0x1000) + +typedef struct system_info_t { + std::string isa; + int pmpregions; + uint64_t mem0_base; + uint64_t mem0_size; + int nharts; + std::vector bootrom; +}; + +system_info_t* info = NULL; +sim_t* sim = NULL; +reg_t tohost_addr = 0; +reg_t fromhost_addr = 0; +std::set magic_addrs; +cfg_t* cfg; + +static std::vector> make_mems(const std::vector &layout) +{ + std::vector> mems; + mems.reserve(layout.size()); + for (const auto &cfg : layout) { + mems.push_back(std::make_pair(cfg.get_base(), new mem_t(cfg.get_size()))); + } + return mems; +} + +extern "C" void cospike_set_sysinfo(char* isa, int pmpregions, + long long int mem0_base, long long int mem0_size, + int nharts, + char* bootrom + ) { + if (!info) { + info = new system_info_t; + info->isa = std::string(isa); + info->pmpregions = pmpregions; + info->mem0_base = mem0_base; + info->mem0_size = mem0_size; + info->nharts = nharts; + std::stringstream ss(bootrom); + std::string s; + while (ss >> s) { + info->bootrom.push_back(std::stoi(s)); + } + } +} + +extern "C" void cospike_cosim(long long int cycle, + long long int hartid, + int has_wdata, + int valid, + long long int iaddr, + unsigned long int insn, + int raise_exception, + int raise_interrupt, + unsigned long long int cause, + unsigned long long int wdata) +{ + assert(info); + if (!sim) { + printf("Configuring spike cosim\n"); + std::vector mem_cfg; + std::vector hartids; + mem_cfg.push_back(mem_cfg_t(info->mem0_base, info->mem0_size)); + for (int i = 0; i < info->nharts; i++) + hartids.push_back(i); + + cfg = new cfg_t(std::make_pair(0, 0), + nullptr, + info->isa.c_str(), + "MSU", + "vlen:128,elen:64", + false, + endianness_little, + info->pmpregions, + mem_cfg, + hartids, + false, + 0 + ); + + std::vector> mems = make_mems(cfg->mem_layout()); + + rom_device_t *boot_rom = new rom_device_t(info->bootrom); + mem_t *boot_addr_reg = new mem_t(0x1000); + uint64_t default_boot_addr = 0x80000000; + boot_addr_reg->store(0, 8, (const uint8_t*)(&default_boot_addr)); + + // Don't actually build a clint + mem_t* clint_mem = new mem_t(CLINT_SIZE); + + std::vector> plugin_devices; + // The device map is hardcoded here for now + plugin_devices.push_back(std::pair(0x4000, boot_addr_reg)); + plugin_devices.push_back(std::pair(0x10000, boot_rom)); + plugin_devices.push_back(std::pair(CLINT_BASE, clint_mem)); + + s_vpi_vlog_info vinfo; + if (!vpi_get_vlog_info(&vinfo)) + abort(); + std::vector htif_args; + bool in_permissive = false; + bool cospike_debug = false; + for (int i = 1; i < vinfo.argc; i++) { + std::string arg(vinfo.argv[i]); + if (arg == "+permissive") { + in_permissive = true; + } else if (arg == "+permissive-off") { + in_permissive = false; + } else if (arg == "+cospike_debug") { + cospike_debug = true; + } else if (!in_permissive) { + htif_args.push_back(arg); + } + } + + debug_module_config_t dm_config = { + .progbufsize = 2, + .max_sba_data_width = 0, + .require_authentication = false, + .abstract_rti = 0, + .support_hasel = true, + .support_abstract_csr_access = true, + .support_abstract_fpr_access = true, + .support_haltgroups = true, + .support_impebreak = true + }; + + printf("%s\n", info->isa.c_str()); + for (int i = 0; i < htif_args.size(); i++) { + printf("%s\n", htif_args[i].c_str()); + } + + sim = new sim_t(cfg, false, + mems, + plugin_devices, + htif_args, + dm_config, + nullptr, + false, + nullptr, + false, + nullptr + ); + + sim->configure_log(true, true); + // Use our own reset vector + for (int i = 0; i < info->nharts; i++) { + sim->get_core(hartid)->get_state()->pc = 0x10040; + } + sim->set_debug(cospike_debug); + printf("Setting up htif for spike cosim\n"); + ((htif_t*)sim)->start(); + printf("Spike cosim started\n"); + tohost_addr = ((htif_t*)sim)->get_tohost_addr(); + fromhost_addr = ((htif_t*)sim)->get_fromhost_addr(); + printf("Tohost : %lx\n", tohost_addr); + printf("Fromhost: %lx\n", fromhost_addr); + } + + processor_t* p = sim->get_core(hartid); + state_t* s = p->get_state(); + uint64_t s_pc = s->pc; + if (raise_interrupt) { + printf("%d interrupt %lx\n", cycle, cause); + uint64_t interrupt_cause = cause & 0x7FFFFFFFFFFFFFFF; + if (interrupt_cause == 3) { + s->mip->backdoor_write_with_mask(MIP_MSIP, MIP_MSIP); + } else { + printf("Unknown interrupt %lx\n", interrupt_cause); + } + } + if (raise_exception) + printf("%d exception %lx\n", cycle, cause); + if (valid) { + printf("%d Cosim: %lx", cycle, iaddr); + if (has_wdata) { + printf(" %lx", wdata); + } + printf("\n"); + } + if (valid || raise_interrupt || raise_exception) + p->step(1); + + if (valid) { + if (s_pc != iaddr) { + printf("%d PC mismatch %lx != %lx\n", cycle, s_pc, iaddr); + exit(1); + } + + // Try to remember magic_mem addrs, and ignore these in the future + auto& mem_write = s->log_mem_write; + if (!mem_write.empty() && tohost_addr && std::get<0>(mem_write[0]) == tohost_addr) { + reg_t wdata = std::get<1>(mem_write[0]); + if (wdata >= info->mem0_base && wdata < (info->mem0_base + info->mem0_size)) { + printf("Probable magic mem %x\n", wdata); + magic_addrs.insert(wdata); + } + } + + if (has_wdata) { + auto& log = s->log_reg_write; + auto& mem_read = s->log_mem_read; + reg_t mem_read_addr = mem_read.empty() ? 0 : std::get<0>(mem_read[0]); + for (auto regwrite : log) { + int rd = regwrite.first >> 4; + int type = regwrite.first & 0xf; + // 0 => int + // 1 => fp + // 2 => vec + // 3 => vec hint + // 4 => csr + if ((rd != 0 && type == 0) || type == 1) { + // Override reads from some CSRs + uint64_t csr_addr = (insn >> 20) & 0xfff; + bool csr_read = (insn & 0x7f) == 0x73; + if (csr_read) printf("CSR read %lx\n", csr_addr); + if (csr_read && ( + (csr_addr == 0xf13) || // mimpid + (csr_addr == 0xf12) || // marchid + (csr_addr == 0xf11) || // mvendorid + (csr_addr == 0xb00) || // mcycle + (csr_addr == 0xb02) || // minstret + (csr_addr >= 0x3b0 && csr_addr <= 0x3ef) // pmpaddr + )) { + printf("CSR override\n"); + s->XPR.write(rd, wdata); + } else if (!mem_read.empty() && ((magic_addrs.count(mem_read_addr) || + (tohost_addr && mem_read_addr == tohost_addr) || + (fromhost_addr && mem_read_addr == fromhost_addr) || + (CLINT_BASE <= mem_read_addr && mem_read_addr < (CLINT_BASE + CLINT_SIZE)) + ))) { + // Don't check reads from tohost, reads from magic memory, or reads from clint + // Technically this could be buggy because log_mem_read only reports vaddrs, but + // no software ever should access tohost/fromhost/clint with vaddrs anyways + printf("Read override %lx\n", mem_read_addr); + s->XPR.write(rd, wdata); + } else if (wdata != regwrite.second.v[0]) { + printf("%d wdata mismatch reg %d %lx != %lx\n", cycle, rd, regwrite.second.v[0], wdata); + exit(1); + } + } + } + } + } +} +// } diff --git a/generators/chipyard/src/main/resources/vsrc/cospike.v b/generators/chipyard/src/main/resources/vsrc/cospike.v new file mode 100644 index 0000000000..f9d2322c54 --- /dev/null +++ b/generators/chipyard/src/main/resources/vsrc/cospike.v @@ -0,0 +1,74 @@ +import "DPI-C" function void cospike_set_sysinfo( + input string isa, + input int pmpregions, + input longint mem0_base, + input longint mem0_size, + input int nharts, + input string bootrom + ); + +import "DPI-C" function void cospike_cosim(input longint cycle, + input longint hartid, + input bit has_wdata, + input bit valid, + input longint iaddr, + input int insn, + input bit raise_exception, + input bit raise_interrupt, + input longint cause, + input longint wdata + ); + + +module SpikeCosim #( + parameter ISA, + parameter PMPREGIONS, + parameter MEM0_BASE, + parameter MEM0_SIZE, + parameter NHARTS, + parameter BOOTROM) ( + input clock, + input reset, + + input [63:0] cycle, + + input [63:0] hartid, + + input trace_0_valid, + input [63:0] trace_0_iaddr, + input [31:0] trace_0_insn, + input trace_0_exception, + input trace_0_interrupt, + input [63:0] trace_0_cause, + input trace_0_has_wdata, + input [63:0] trace_0_wdata, + + input trace_1_valid, + input [63:0] trace_1_iaddr, + input [31:0] trace_1_insn, + input trace_1_exception, + input trace_1_interrupt, + input [63:0] trace_1_cause, + input trace_1_has_wdata, + input [63:0] trace_1_wdata + ); + + initial begin + cospike_set_sysinfo(ISA, PMPREGIONS, MEM0_BASE, MEM0_SIZE, NHARTS, BOOTROM); + end; + + always @(posedge clock) begin + if (!reset) begin + if (trace_0_valid || trace_0_exception || trace_0_cause) begin + cospike_cosim(cycle, hartid, trace_0_has_wdata, trace_0_valid, trace_0_iaddr, + trace_0_insn, trace_0_exception, trace_0_interrupt, trace_0_cause, + trace_0_wdata); + end + if (trace_1_valid || trace_1_exception || trace_1_cause) begin + cospike_cosim(cycle, hartid, trace_1_has_wdata, trace_1_valid, trace_1_iaddr, + trace_1_insn, trace_1_exception, trace_1_interrupt, trace_1_cause, + trace_1_wdata); + end + end + end +endmodule; // CospikeCosim diff --git a/generators/chipyard/src/main/scala/Cospike.scala b/generators/chipyard/src/main/scala/Cospike.scala new file mode 100644 index 0000000000..7b663b2455 --- /dev/null +++ b/generators/chipyard/src/main/scala/Cospike.scala @@ -0,0 +1,88 @@ +package chipyard + +import chisel3._ +import chisel3.experimental.{IntParam, StringParam, IO} +import chisel3.util._ + +import freechips.rocketchip.config.{Parameters, Field, Config} +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.util._ + +import testchipip.TileTraceIO + +case class SpikeCosimConfig( + isa: String, + pmpregions: Int, + mem0_base: BigInt, + mem0_size: BigInt, + nharts: Int, + bootrom: String +) + +class SpikeCosim(cfg: SpikeCosimConfig) extends BlackBox(Map( + "ISA" -> StringParam(cfg.isa), + "PMPREGIONS" -> IntParam(cfg.pmpregions), + "MEM0_BASE" -> IntParam(cfg.mem0_base), + "MEM0_SIZE" -> IntParam(cfg.mem0_size), + "NHARTS" -> IntParam(cfg.nharts), + "BOOTROM" -> StringParam(cfg.bootrom) +)) with HasBlackBoxResource +{ + addResource("/csrc/cospike.cc") + addResource("/vsrc/cospike.v") + val io = IO(new Bundle { + val clock = Input(Clock()) + val reset = Input(Bool()) + val cycle = Input(UInt(64.W)) + val hartid = Input(UInt(64.W)) + val trace = Input(Vec(2, new Bundle { + val valid = Bool() + val iaddr = UInt(64.W) + val insn = UInt(32.W) + val exception = Bool() + val interrupt = Bool() + val cause = UInt(64.W) + val has_wdata = Bool() + val wdata = UInt(64.W) + })) + }) +} + +object SpikeCosim +{ + def apply(trace: TileTraceIO, hartid: Int, cfg: SpikeCosimConfig) = { + val cosim = Module(new SpikeCosim(cfg)) + val cycle = withClockAndReset(trace.clock, trace.reset) { + val r = RegInit(0.U(64.W)) + r := r + 1.U + r + } + cosim.io.clock := trace.clock + cosim.io.reset := trace.reset + require(trace.numInsns <= 2) + cosim.io.cycle := cycle + cosim.io.trace.map(t => { + t.valid := false.B + t.iaddr := 0.U + t.insn := 0.U + t.exception := false.B + t.interrupt := false.B + t.cause := 0.U + }) + cosim.io.hartid := hartid.U + for (i <- 0 until trace.numInsns) { + cosim.io.trace(i).valid := trace.insns(i).valid + val signed = Wire(SInt(64.W)) + signed := trace.insns(i).iaddr.asSInt + cosim.io.trace(i).iaddr := signed.asUInt + cosim.io.trace(i).insn := trace.insns(i).insn + cosim.io.trace(i).exception := trace.insns(i).exception + cosim.io.trace(i).interrupt := trace.insns(i).interrupt + cosim.io.trace(i).cause := trace.insns(i).cause + cosim.io.trace(i).has_wdata := trace.insns(i).wdata.isDefined.B + cosim.io.trace(i).wdata := trace.insns(i).wdata.getOrElse(0.U) + } + } +} diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 5ff78a65d5..a47b08e0db 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -21,7 +21,7 @@ import barstools.iocell.chisel._ import testchipip._ -import chipyard.{HasHarnessSignalReferences, HarnessClockInstantiatorKey} +import chipyard._ import chipyard.clocking.{HasChipyardPRCI} import chipyard.iobinders.{GetSystemParameters, JTAGChipIO, ClockWithFreq} @@ -333,6 +333,24 @@ class WithSimDromajoBridge extends ComposeHarnessBinder({ } }) +class WithCospike extends ComposeHarnessBinder({ + (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => { + implicit val p = chipyard.iobinders.GetSystemParameters(system) + val chipyardSystem = system.asInstanceOf[ChipyardSystemModule[_]].outer.asInstanceOf[ChipyardSystem] + val tiles = chipyardSystem.tiles + val cfg = SpikeCosimConfig( + isa = tiles.headOption.map(_.isaDTS).getOrElse(""), + mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)), + mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)), + pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0), + nharts = tiles.size, + bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse("") + ) + ports.map { p => p.traces.zipWithIndex.map(t => SpikeCosim(t._1, t._2, cfg)) } + } +}) + + class WithCustomBootPinPlusArg extends OverrideHarnessBinder({ (system: CanHavePeripheryCustomBootPin, th: HasHarnessSignalReferences, ports: Seq[Bool]) => { val pin = PlusArg("custom_boot_pin", width=1) diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala index 44a6229aa9..c7e5b69d9c 100644 --- a/generators/chipyard/src/main/scala/SpikeTile.scala +++ b/generators/chipyard/src/main/scala/SpikeTile.scala @@ -16,7 +16,6 @@ import freechips.rocketchip.tile._ import freechips.rocketchip.prci.ClockSinkParameters case class SpikeCoreParams( - val maxInsnsPerCycle: Int = 10000 ) extends CoreParams { val useVM = true val useHypervisor = false @@ -305,23 +304,29 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) { spike.io.msip := int_bundle.msip spike.io.meip := int_bundle.meip spike.io.seip := int_bundle.seip.get - spike.io.ipc := outer.spikeTileParams.core.maxInsnsPerCycle.U + spike.io.ipc := PlusArg("spike-ipc", 10000, width=64) val blockBits = log2Ceil(p(CacheBlockBytes)) - spike.io.icache.a.ready := icache_tl.a.ready - icache_tl.a.valid := spike.io.icache.a.valid - icache_tl.a.bits := icacheEdge.Get( + + val icache_a_q = Module(new Queue(new TLBundleA(icacheEdge.bundle), 1, flow=true, pipe=true)) + spike.io.icache.a.ready := icache_a_q.io.enq.ready && icache_a_q.io.count === 0.U + icache_tl.a <> icache_a_q.io.deq + icache_a_q.io.enq.valid := spike.io.icache.a.valid + icache_a_q.io.enq.bits := icacheEdge.Get( fromSource = spike.io.icache.a.sourceid, toAddress = (spike.io.icache.a.address >> blockBits) << blockBits, lgSize = blockBits.U)._2 + icache_tl.d.ready := true.B spike.io.icache.d.valid := icache_tl.d.valid spike.io.icache.d.sourceid := icache_tl.d.bits.source spike.io.icache.d.data := icache_tl.d.bits.data.asTypeOf(Vec(8, UInt(64.W))) - spike.io.dcache.a.ready := dcache_tl.a.ready - dcache_tl.a.valid := spike.io.dcache.a.valid - dcache_tl.a.bits := dcacheEdge.AcquireBlock( + val dcache_a_q = Module(new Queue(new TLBundleA(dcacheEdge.bundle), 1, flow=true, pipe=true)) + spike.io.dcache.a.ready := dcache_a_q.io.enq.ready && dcache_a_q.io.count === 0.U + dcache_tl.a <> dcache_a_q.io.deq + dcache_a_q.io.enq.valid := spike.io.dcache.a.valid + dcache_a_q.io.enq.bits := dcacheEdge.AcquireBlock( fromSource = spike.io.dcache.a.sourceid, toAddress = (spike.io.dcache.a.address >> blockBits) << blockBits, lgSize = blockBits.U, @@ -333,9 +338,11 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) { spike.io.dcache.b.source := dcache_tl.b.bits.source spike.io.dcache.b.param := dcache_tl.b.bits.param - spike.io.dcache.c.ready := dcache_tl.c.ready - dcache_tl.c.valid := spike.io.dcache.c.valid - dcache_tl.c.bits := Mux(spike.io.dcache.c.voluntary, + val dcache_c_q = Module(new Queue(new TLBundleC(dcacheEdge.bundle), 1, flow=true, pipe=true)) + spike.io.dcache.c.ready := dcache_c_q.io.enq.ready && dcache_c_q.io.count === 0.U + dcache_tl.c <> dcache_c_q.io.deq + dcache_c_q.io.enq.valid := spike.io.dcache.c.valid + dcache_c_q.io.enq.bits := Mux(spike.io.dcache.c.voluntary, dcacheEdge.Release( fromSource = spike.io.dcache.c.sourceid, toAddress = spike.io.dcache.c.address, @@ -369,10 +376,12 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) { dcache_tl.e.valid := dcache_tl.d.valid && should_finish dcache_tl.e.bits := dcacheEdge.GrantAck(dcache_tl.d.bits) - spike.io.mmio.a.ready := mmio_tl.a.ready - mmio_tl.a.valid := spike.io.mmio.a.valid + val mmio_a_q = Module(new Queue(new TLBundleA(mmioEdge.bundle), 1, flow=true, pipe=true)) + spike.io.mmio.a.ready := mmio_a_q.io.enq.ready && mmio_a_q.io.count === 0.U + mmio_tl.a <> mmio_a_q.io.deq + mmio_a_q.io.enq.valid := spike.io.mmio.a.valid val log_size = MuxCase(0.U, (0 until 3).map { i => (spike.io.mmio.a.size === (1 << i).U) -> i.U }) - mmio_tl.a.bits := Mux(spike.io.mmio.a.store, + mmio_a_q.io.enq.bits := Mux(spike.io.mmio.a.store, mmioEdge.Put(0.U, spike.io.mmio.a.address, log_size, spike.io.mmio.a.data)._2, mmioEdge.Get(0.U, spike.io.mmio.a.address, log_size)._2) diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala index bbc816f77c..da224a9b3c 100644 --- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -54,3 +54,9 @@ class DromajoBoomConfig extends Config( new boom.common.WithNSmallBooms(1) ++ new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig) + +class MediumBoomCosimConfig extends Config( + new chipyard.harness.WithCospike ++ // attach spike-cosim + new chipyard.config.WithTraceIO ++ // enable the traceio + new boom.common.WithNMediumBooms(1) ++ + new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala index eac274f090..f19759cb46 100644 --- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala @@ -9,7 +9,6 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams import boom.common.{BoomTileAttachParams} import cva6.{CVA6TileAttachParams} - import testchipip._ class WithL2TLBs(entries: Int) extends Config((site, here, up) => { @@ -79,3 +78,4 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => { )) } }) + diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index 461767199a..e7d6aff19a 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 461767199aac9c15894513254ae4844de5ee78d0 +Subproject commit e7d6aff19a071a059f1b9c2328ee4dac83bc677a