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It would be great if the tester could peek/poke FIRRTL circuits. Also, it would be nice to use it to test IOs which a FIRRTL transform added, which doesn't have a Chisel equivalent.
I'd recommend looking at FIRRTL's
I think that makes sense, though I do want to keep the chisel-level circuit interface API. So some kind of shim for a FIRRTL circuit would be needed to provide the interface definition for testers2. It could be manually written, or auto-generated.
For post-syn/post-par, testers2 already uses a name mapping table to translate the circuit interface data structures (Chisel hardware objects) to the handle needed by the underlying tester. If the IO structure is mostly the same this should also extend to post-syn/post-par, with potentially more top-level flow options needed to select what (eg particular Verilog files / simulator) to test?