diff --git a/src/main/scala/Verilog.scala b/src/main/scala/Verilog.scala
index 9b0164af..a2e5a42d 100644
--- a/src/main/scala/Verilog.scala
+++ b/src/main/scala/Verilog.scala
@@ -302,13 +302,15 @@ class VerilogBackend extends Backend {
           def find_gran(x: Node) : Int = {
             if (x.isInstanceOf[Literal])
               return x.width
+            else if (x.isInstanceOf[UInt])
+              return find_gran(x.inputs(0))
             else if (x.isInstanceOf[Op])
               return (x.inputs.map(find_gran(_))).reduceLeft(_ max _)
             else
-              return -1
+              return 1
           }
           val mask_writers = m.writeAccesses.filter(_.isMasked)
-          val mask_grans = mask_writers.map(x => find_gran(x.mask.inputs(0)))
+          val mask_grans = mask_writers.map(x => find_gran(x.mask))
           val mask_gran = if (!mask_grans.isEmpty && mask_grans.forall(_ == mask_grans(0))) mask_grans(0) else 1
           val configStr =
           (" depth " + m.n +