From 8b30e186bcbf56549204b0e9800bd4f23228d8f7 Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Mon, 3 Dec 2018 22:32:18 -0800 Subject: [PATCH] Integrate Hwacha for initial public release --- .gitmodules | 10 ++ Makefrag | 66 +++++------ Makefrag-variables | 37 +++++++ README.md | 59 +++++++--- build.sbt | 6 +- hwacha | 1 + project/build.properties | 1 + riscv-tools | 1 + scripts/check_commit_log | 160 +++++++++++++++++++++++++++ scripts/init-submodules | 10 ++ src/main/scala/example/Configs.scala | 16 +-- src/main/scala/example/PWM.scala | 93 ---------------- src/main/scala/example/Top.scala | 8 -- torture | 1 + verisim/Makefile | 54 +++------ verisim/Makefrag-verilator | 13 +-- vsim/Makefile | 48 +++----- 17 files changed, 343 insertions(+), 241 deletions(-) create mode 100644 Makefrag-variables create mode 160000 hwacha create mode 100644 project/build.properties create mode 160000 riscv-tools create mode 100755 scripts/check_commit_log create mode 100755 scripts/init-submodules delete mode 100644 src/main/scala/example/PWM.scala create mode 160000 torture diff --git a/.gitmodules b/.gitmodules index eda0fac..b7e6ee4 100644 --- a/.gitmodules +++ b/.gitmodules @@ -4,3 +4,13 @@ [submodule "testchipip"] path = testchipip url = https://github.com/ucb-bar/testchipip.git +[submodule "hwacha"] + path = hwacha + url = https://github.com/ucb-bar/hwacha.git +[submodule "esp-tools"] + path = riscv-tools + url = https://github.com/ucb-bar/esp-tools.git +[submodule "torture"] + path = torture + url = https://github.com/ucb-bar/riscv-torture.git + branch = hwacha diff --git a/Makefrag b/Makefrag index 62f6efc..b4b112f 100644 --- a/Makefrag +++ b/Makefrag @@ -1,6 +1,6 @@ ROCKETCHIP_DIR=$(base_dir)/rocket-chip -SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++2.12.4 +SBT ?= java -Xmx$(JVM_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++2.12.4 lookup_scala_srcs = $(shell find $(1)/ -iname "*.scala" 2> /dev/null) @@ -9,7 +9,7 @@ SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/$(p ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/target/scala-2.12/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-2.12/*" FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar -FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(ROCKET_CLASSES):$(FIRRTL_JAR) firrtl.Driver +FIRRTL ?= java -Xmx$(JVM_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M -cp $(ROCKET_CLASSES):$(FIRRTL_JAR) firrtl.Driver $(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala) $(MAKE) -C $(ROCKETCHIP_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKETCHIP_DIR)/firrtl build-scala @@ -24,47 +24,41 @@ include $(testchip_dir)/Makefrag CHISEL_ARGS ?= -FIRRTL_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir -ANNO_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).anno.json -VERILOG_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v +FIRRTL_FILE=$(build_dir)/$(long_name).fir +ANNO_FILE=$(build_dir)/$(long_name).anno.json +VERILOG_FILE=$(build_dir)/$(long_name).v $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(bootrom_img) $(FIRRTL_JAR) mkdir -p $(build_dir) - cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" + cd $(base_dir) && $(SBT) "runMain $(GENERATOR_PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" $(VERILOG_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(FIRRTL_JAR) $(FIRRTL) -i $(FIRRTL_FILE) -o $(VERILOG_FILE) -X verilog -faf $(ANNO_FILE) -regression-tests = \ - rv64ud-v-fcvt \ - rv64ud-p-fdiv \ - rv64ud-v-fadd \ - rv64uf-v-fadd \ - rv64um-v-mul \ - rv64mi-p-breakpoint \ - rv64uc-v-rvc \ - rv64ud-v-structural \ - rv64si-p-wfi \ - rv64um-v-divw \ - rv64ua-v-lrsc \ - rv64ui-v-fence_i \ - rv64ud-v-fcvt_w \ - rv64uf-v-fmin \ - rv64ui-v-sb \ - rv64ua-v-amomax_d \ - rv64ud-v-move \ - rv64ud-v-fclass \ - rv64ua-v-amoand_d \ - rv64ua-v-amoxor_d \ - rv64si-p-sbreak \ - rv64ud-v-fmadd \ - rv64uf-v-ldst \ - rv64um-v-mulh \ - rv64si-p-dirty - output_dir=$(sim_dir)/output -$(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% - mkdir -p $(output_dir) - ln -sf $< $@ +# Assembly/Benchmark Testing +.PRECIOUS: $(output_dir)/%.vpd + +$(output_dir)/%.run: $(output_dir)/% $(sim) + cd $(sim_dir) && $(exec_sim) +max-cycles=$(timeout_cycles) +permissive-off $< 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ] + +$(output_dir)/%.out: $(output_dir)/% $(sim) + cd $(sim_dir) && $(exec_sim) +verbose +max-cycles=$(timeout_cycles) +permissive-off $< $(disasm) $@ && [ $$PIPESTATUS -eq 0 ] + +$(output_dir)/%.vcd: $(output_dir)/% $(sim_debug) + cd $(sim_dir) && $(exec_sim_debug) +verbose -v$@ +max-cycles=$(timeout_cycles) +permissive-off $< $(disasm) $(patsubst %.vcd,%.out,$@) && [ $$PIPESTATUS -eq 0 ] + +$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) + cd $(sim_dir) && $(exec_sim_debug) +verbose +vcdplusfile=$@ +max-cycles=$(timeout_cycles) +permissive-off $< $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ] + +$(output_dir)/%.saif: $(output_dir)/% $(sim_debug) + cd $(sim_dir) && rm -f $(output_dir)/pipe-$*.vcd && vcd2saif -input $(output_dir)/pipe-$*.vcd -pipe "$(exec_sim_debug) +verbose +vcdfile=$(output_dir)/pipe-$*.vcd +max-cycles=$(bmark_timeout_cycles) +permissive-off $<" -output $@ > $(patsubst %.saif,%.out,$@) 2>&1 + +run: run-asm-tests run-bmark-tests +run-debug: run-asm-tests-debug run-bmark-tests-debug +run-fast: run-asm-tests-fast run-bmark-tests-fast +.PHONY: run-asm-tests run-bmark-tests +.PHONY: run-asm-tests-debug run-bmark-tests-debug +.PHONY: run run-debug run-fast diff --git a/Makefrag-variables b/Makefrag-variables new file mode 100644 index 0000000..b30557b --- /dev/null +++ b/Makefrag-variables @@ -0,0 +1,37 @@ +PROJECT ?= freechips.rocketchip.system +MODEL ?= TestHarness +CONFIG ?= ISCA2016Config +CFG_PROJECT ?= hwacha +GENERATOR_PROJECT ?= hwacha +TB ?= TestDriver + +JVM_HEAP_SIZE ?= 16G + +long_name = $(PROJECT).$(CONFIG) + +rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc +rocketchip_csrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/csrc + +sim_vsrcs = \ + $(VERILOG_FILE) \ + $(rocketchip_vsrc_dir)/$(TB).v \ + $(rocketchip_vsrc_dir)/AsyncResetReg.v \ + $(rocketchip_vsrc_dir)/plusarg_reader.v \ + $(rocketchip_vsrc_dir)/SimDTM.v \ + $(testchip_vsrcs) + +sim_csrcs = \ + $(testchip_csrcs) \ + $(rocketchip_csrc_dir)/SimDTM.cc + +# Assembly/Benchmark Testing +disasm := 2> +which_disasm := $(shell which spike-dasm 2> /dev/null) +ifneq ($(which_disasm),) + disasm = 3>&1 1>&2 2>&3 | $(which_disasm) $(DISASM_EXTENSION) > +endif + +timeout_cycles = 10000000 +bmark_timeout_cycles = 100000000 + +junk += $(output_dir) diff --git a/README.md b/README.md index 8d45685..b6dd83f 100644 --- a/README.md +++ b/README.md @@ -1,8 +1,20 @@ -# RISC-V Project Template +# UCB-BAR Hwacha Project Template -This is a starter template for your custom RISC-V project. It will allow you -to leverage the Chisel HDL and RocketChip SoC generator to produce a -RISC-V SoC with MMIO-mapped peripherals, DMA, and custom accelerators. +This is a template for building a rocket-chip with Hwacha. + +## Submodules and Subdirectories + +The submodules and subdirectories for the project template are organized as +follows. + + * rocket-chip - contains code for the RocketChip generator, Chisel HCL, and FIRRTL + * hwacha - contains code for the Hwacha accelerator + * riscv-tools - contains the code for the compiler toolchain that targets Hwacha + * testchipip - contains the serial adapter, block device, and associated verilog and C++ code + * verisim - directory in which Verilator simulations are compiled and run + * vsim - directory in which Synopsys VCS simulations are compiled and run + * bootrom - sources for the first-stage bootloader included in the Boot ROM + * src/main/scala - scala source files for your project extension go here ## Getting started @@ -10,9 +22,9 @@ RISC-V SoC with MMIO-mapped peripherals, DMA, and custom accelerators. After cloning this repo, you will need to initialize all of the submodules - git clone https://github.com/ucb-bar/project-template.git - cd project-template - git submodule update --init --recursive + git clone https://github.com/ucb-bar/hwacha-template.git + cd hwacha-template + ./scripts/init-submodules ### Building the tools @@ -38,25 +50,36 @@ An executable called simulator-example-DefaultExampleConfig will be produced. You can then use this executable to run any compatible RV64 code. For instance, to run one of the riscv-tools assembly tests. - ./simulator-example-DefaultExampleConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple + make output/rv64ui-p-simple.out If you later create your own project, you can use environment variables to -build an alternate configuration. +build an alternate configuration. The different variables are + +* PROJECT: The package that contains your test harness class +* CFG_PROJECT: The package that contains your config class +* GENERATOR_PROJECT: The package that contains your Generator class +* MODEL: The class name of your test harness +* CONFIG: The class name of your config + +You can manually override them like this make PROJECT=yourproject CONFIG=YourConfig ./simulator-yourproject-YourConfig ... -## Submodules and Subdirectories +### Running random tests with torture ### -The submodules and subdirectories for the project template are organized as -follows. +RISC-V Torture is included as a submodule and includes the ability to test +Hwacha. +You can run a single test like so: - * rocket-chip - contains code for the RocketChip generator and Chisel HDL - * testchipip - contains the serial adapter, block device, and associated verilog and C++ code - * verisim - directory in which Verilator simulations are compiled and run - * vsim - directory in which Synopsys VCS simulations are compiled and run - * bootrom - sources for the first-stage bootloader included in the Boot ROM - * src/main/scala - scala source files for your project go here + make rgentest R_SIM=../vsim/simv-freechips.rocketchip.chip-ISCA2016Config + +You can run a nightly test, which runs for a set amount of time or a set +number of failures like this: + + make rnight R_SIM=../vsim/simv-freechips.rocketchip.chip-ISCA2016Config OPTIONS="-C config/mem_vec.config -t 5 -m 30" + +## THE REMAINDER OF THIS FILE IS COPIED FROM PROJECT-TEMPLATE ## ## Using the block device diff --git a/build.sbt b/build.sbt index 5e8e7e0..4301dca 100644 --- a/build.sbt +++ b/build.sbt @@ -15,6 +15,8 @@ lazy val commonSettings = Seq( lazy val rocketchip = RootProject(file("rocket-chip")) -lazy val testchipip = project.settings(commonSettings).dependsOn(rocketchip) +lazy val testchipip = project.settings(commonSettings:_*).dependsOn(rocketchip) -lazy val example = (project in file(".")).settings(commonSettings).dependsOn(testchipip) +lazy val hwacha = project.settings(commonSettings:_*).dependsOn(rocketchip) + +lazy val example = (project in file(".")).settings(commonSettings:_*).dependsOn(testchipip, hwacha) diff --git a/hwacha b/hwacha new file mode 160000 index 0000000..a467ae8 --- /dev/null +++ b/hwacha @@ -0,0 +1 @@ +Subproject commit a467ae81a4b89da26e60d8ab684763841566b062 diff --git a/project/build.properties b/project/build.properties new file mode 100644 index 0000000..31334bb --- /dev/null +++ b/project/build.properties @@ -0,0 +1 @@ +sbt.version=1.1.1 diff --git a/riscv-tools b/riscv-tools new file mode 160000 index 0000000..abb8f01 --- /dev/null +++ b/riscv-tools @@ -0,0 +1 @@ +Subproject commit abb8f0134b34a4f1b915e96988c410691c33de7d diff --git a/scripts/check_commit_log b/scripts/check_commit_log new file mode 100755 index 0000000..374a330 --- /dev/null +++ b/scripts/check_commit_log @@ -0,0 +1,160 @@ +#! /usr/bin/env python + +import sys +from sets import Set + +if len(sys.argv) < 3: + print "usage: %s " % sys.argv[0] + exit(-1) + +slog = map(lambda x: x.strip(), open(sys.argv[1]).readlines()) +vlog = map(lambda x: x.strip(), open(sys.argv[2]).readlines()) + +spike_arf = {} +spike_srf = {} +spike_vrf = {} +spike_prf = {} +vsim_arf = {} +vsim_srf = {} +vsim_vrf = {} +vsim_prf = {} + +nvdpr = 256 +nppr = 16 +nlanes = 1 +lstride = 1 +lstrip = 1< c: + diverged = True + print l + cycle = c + except IndexError: + print "not matching number of writes" + print "vsim", v + print "spike", s + +compare_keys('arf', spike_arf, vsim_arf) +for addr in sorted(vsim_arf.keys()): + compare_data('arf[%02d]' % addr, spike_arf[addr], vsim_arf[addr]) + +compare_keys('srf', spike_srf, vsim_srf) +for addr in sorted(vsim_srf.keys()): + if addr != 0: + compare_data('srf[%02d]' % addr, spike_srf[addr], vsim_srf[addr]) + +compare_keys('vrf', spike_vrf, vsim_vrf) +for eidx in sorted(vsim_vrf.keys()): + try: + compare_keys('vrf[%02d]' % eidx, spike_vrf[eidx], vsim_vrf[eidx]) + for addr in sorted(vsim_vrf[eidx].keys()): + compare_data('vrf[%02d][%03d]' % (eidx, addr), spike_vrf[eidx][addr], vsim_vrf[eidx][addr]) + except KeyError: + print "something is very wrong with", eidx, addr + +compare_keys('prf', spike_prf, vsim_prf) +for eidx in sorted(vsim_prf.keys()): + try: + compare_keys('prf[%02d]' % eidx, spike_prf[eidx], vsim_prf[eidx]) + for addr in sorted(vsim_prf[eidx].keys()): + compare_data('prf[%02d][%02d]' % (eidx, addr), spike_prf[eidx][addr], vsim_prf[eidx][addr]) + except KeyError: + print "something is very wrong with", eidx, addr + +if diverged: + print "DOESN'T MATCH: earliest cycle", cycle +else: + print "ZARRO BOOGS FOUND" diff --git a/scripts/init-submodules b/scripts/init-submodules new file mode 100755 index 0000000..bc9d97d --- /dev/null +++ b/scripts/init-submodules @@ -0,0 +1,10 @@ +#! /bin/bash + +# top-level +git submodule update --init rocket-chip riscv-tools testchipip hwacha torture +# rocket-chip (skip tools) +(cd rocket-chip && git submodule update --init --recursive hardfloat chisel3 firrtl) +# esp-tools (skip llvm) +(cd riscv-tools && git submodule update --init --recursive riscv-isa-sim riscv-fesvr riscv-pk riscv-opcodes riscv-tests riscv-gnu-toolchain riscv-openocd) +# torture submodules +(cd torture && git submodule update --init --recursive) diff --git a/src/main/scala/example/Configs.scala b/src/main/scala/example/Configs.scala index 4c7498c..2057d35 100644 --- a/src/main/scala/example/Configs.scala +++ b/src/main/scala/example/Configs.scala @@ -7,6 +7,7 @@ import freechips.rocketchip.diplomacy.{LazyModule, ValName} import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.tile.XLen import testchipip._ +import hwacha._ class WithBootROM extends Config((site, here, up) => { case BootROMParams => BootROMParams( @@ -24,11 +25,6 @@ class WithExampleTop extends Config((site, here, up) => { } }) -class WithPWM extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new ExampleTopWithPWM()(p)).module) -}) - class WithBlockDeviceModel extends Config((site, here, up) => { case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => { val top = Module(LazyModule(new ExampleTopWithBlockDevice()(p)).module) @@ -45,6 +41,14 @@ class WithSimBlockDevice extends Config((site, here, up) => { } }) +class ExampleHwachaConfig extends Config( + new WithExampleTop ++ + new ISCA2016Config) + +class ExampleHwacha4LaneConfig extends Config( + new WithExampleTop ++ + new ISCA2016L4Config) + class BaseExampleConfig extends Config( new WithBootROM ++ new freechips.rocketchip.system.DefaultConfig) @@ -55,8 +59,6 @@ class DefaultExampleConfig extends Config( class RoccExampleConfig extends Config( new WithRoccExample ++ new DefaultExampleConfig) -class PWMConfig extends Config(new WithPWM ++ new BaseExampleConfig) - class SimBlockDeviceConfig extends Config( new WithBlockDevice ++ new WithSimBlockDevice ++ new BaseExampleConfig) diff --git a/src/main/scala/example/PWM.scala b/src/main/scala/example/PWM.scala deleted file mode 100644 index c2621d3..0000000 --- a/src/main/scala/example/PWM.scala +++ /dev/null @@ -1,93 +0,0 @@ -package example - -import chisel3._ -import chisel3.util._ -import freechips.rocketchip.subsystem.BaseSubsystem -import freechips.rocketchip.config.{Parameters, Field} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.regmapper.{HasRegMap, RegField} -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util.UIntIsOneOf - -case class PWMParams(address: BigInt, beatBytes: Int) - -class PWMBase(w: Int) extends Module { - val io = IO(new Bundle { - val pwmout = Output(Bool()) - val period = Input(UInt(w.W)) - val duty = Input(UInt(w.W)) - val enable = Input(Bool()) - }) - - // The counter should count up until period is reached - val counter = Reg(UInt(w.W)) - - when (counter >= (io.period - 1.U)) { - counter := 0.U - } .otherwise { - counter := counter + 1.U - } - - // If PWM is enabled, pwmout is high when counter < duty - // If PWM is not enabled, it will always be low - io.pwmout := io.enable && (counter < io.duty) -} - -trait PWMTLBundle extends Bundle { - val pwmout = Output(Bool()) -} - -trait PWMTLModule extends HasRegMap { - val io: PWMTLBundle - implicit val p: Parameters - def params: PWMParams - - // How many clock cycles in a PWM cycle? - val period = Reg(UInt(32.W)) - // For how many cycles should the clock be high? - val duty = Reg(UInt(32.W)) - // Is the PWM even running at all? - val enable = RegInit(false.B) - - val base = Module(new PWMBase(32)) - io.pwmout := base.io.pwmout - base.io.period := period - base.io.duty := duty - base.io.enable := enable - - regmap( - 0x00 -> Seq( - RegField(32, period)), - 0x04 -> Seq( - RegField(32, duty)), - 0x08 -> Seq( - RegField(1, enable))) -} - -class PWMTL(c: PWMParams)(implicit p: Parameters) - extends TLRegisterRouter( - c.address, "pwm", Seq("ucbbar,pwm"), - beatBytes = c.beatBytes)( - new TLRegBundle(c, _) with PWMTLBundle)( - new TLRegModule(c, _, _) with PWMTLModule) - -trait HasPeripheryPWM { this: BaseSubsystem => - implicit val p: Parameters - - private val address = 0x2000 - private val portName = "pwm" - - val pwm = LazyModule(new PWMTL( - PWMParams(address, pbus.beatBytes))(p)) - - pbus.toVariableWidthSlave(Some(portName)) { pwm.node } -} - -trait HasPeripheryPWMModuleImp extends LazyModuleImp { - implicit val p: Parameters - val outer: HasPeripheryPWM - - val pwmout = IO(Output(Bool())) - - pwmout := outer.pwm.module.io.pwmout -} diff --git a/src/main/scala/example/Top.scala b/src/main/scala/example/Top.scala index 4d74ce4..c79b8e6 100644 --- a/src/main/scala/example/Top.scala +++ b/src/main/scala/example/Top.scala @@ -26,14 +26,6 @@ class ExampleTopModule[+L <: ExampleTop](l: L) extends RocketSubsystemModuleImp( with HasPeripherySerialModuleImp with DontTouch -class ExampleTopWithPWM(implicit p: Parameters) extends ExampleTop - with HasPeripheryPWM { - override lazy val module = new ExampleTopWithPWMModule(this) -} - -class ExampleTopWithPWMModule(l: ExampleTopWithPWM) - extends ExampleTopModule(l) with HasPeripheryPWMModuleImp - class ExampleTopWithBlockDevice(implicit p: Parameters) extends ExampleTop with HasPeripheryBlockDevice { override lazy val module = new ExampleTopWithBlockDeviceModule(this) diff --git a/torture b/torture new file mode 160000 index 0000000..54a6420 --- /dev/null +++ b/torture @@ -0,0 +1 @@ +Subproject commit 54a6420e67880b18948e1977d7ff2370fb44f66e diff --git a/verisim/Makefile b/verisim/Makefile index d4ca59a..f9ed845 100644 --- a/verisim/Makefile +++ b/verisim/Makefile @@ -1,14 +1,11 @@ base_dir=$(abspath ..) sim_dir=$(abspath .) -PROJECT ?= example -MODEL ?= TestHarness -CONFIG ?= DefaultExampleConfig -CFG_PROJECT ?= $(PROJECT) -TB ?= TestDriver - +include $(base_dir)/Makefrag-variables sim = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG) sim_debug = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG)-debug +tether_file = $(build_dir)/$(CONFIG).tether +TETHER ?= dtm default: $(sim) @@ -19,20 +16,12 @@ LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesv include $(base_dir)/Makefrag include $(sim_dir)/Makefrag-verilator +ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),) +-include $(build_dir)/$(long_name).d +endif -long_name = $(PROJECT).$(MODEL).$(CONFIG) - -rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc - -sim_vsrcs = \ - $(build_dir)/$(long_name).v \ - $(rocketchip_vsrc_dir)/AsyncResetReg.v \ - $(rocketchip_vsrc_dir)/plusarg_reader.v \ - $(testchip_vsrcs) - -sim_csrcs = \ - $(sim_dir)/csrc/verilator-harness.cc \ - $(testchip_csrcs) +sim_csrcs += \ + $(sim_dir)/csrc/verilator-harness.cc model_dir = $(build_dir)/$(long_name) model_dir_debug = $(build_dir)/$(long_name).debug @@ -46,9 +35,10 @@ model_mk_debug = $(model_dir_debug)/V$(MODEL).mk $(model_mk): $(sim_vsrcs) $(INSTALLED_VERILATOR) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name) + $(if $(wildcard $(tether_file)),$(eval TETHER := tsi)) $(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \ -o $(sim) $< $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \ - -CFLAGS "-I$(build_dir) -include $(model_header)" + -CFLAGS "-I$(build_dir) -DTETHER_TYPE=$(TETHER)_t -DTETHER_NAME=$(TETHER) -include $(model_header)" touch $@ $(sim): $(model_mk) $(sim_csrcs) @@ -57,30 +47,20 @@ $(sim): $(model_mk) $(sim_csrcs) $(model_mk_debug): $(sim_vsrcs) $(INSTALLED_VERILATOR) mkdir -p $(build_dir)/$(long_name).debug + $(if $(wildcard $(tether_file)),$(eval TETHER := tsi)) $(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \ -o $(sim_debug) $< $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \ - -CFLAGS "-I$(build_dir) -include $(model_header_debug)" + -CFLAGS "-I$(build_dir) -DTETHER_TYPE=$(TETHER)_t -DTETHER_NAME=$(TETHER) -include $(model_header_debug)" touch $@ $(sim_debug): $(model_mk_debug) $(sim_csrcs) $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk -$(output_dir)/%.out: $(output_dir)/% $(sim) - $(sim) +verbose +max-cycles=1000000 $< 3>&1 1>&2 2>&3 | spike-dasm > $@ - -$(output_dir)/%.run: $(output_dir)/% $(sim) - $(sim) +max-cycles=1000000 $< && touch $@ -$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) - rm -f $@.vcd && mkfifo $@.vcd - vcd2vpd $@.vcd $@ > /dev/null & - $(sim_debug) -v$@.vcd +max-cycles=1000000 $< - -run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests))) - -run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests))) - -run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests))) +exec_sim = $(sim) +exec_sim_debug = $(sim_debug) clean: - rm -rf generated-src ./simulator-* + rm -rf $(build_dir) ./simulator-* + +.PHONY: clean default debug diff --git a/verisim/Makefrag-verilator b/verisim/Makefrag-verilator index b16cd60..408cd22 100644 --- a/verisim/Makefrag-verilator +++ b/verisim/Makefrag-verilator @@ -24,14 +24,13 @@ verilator/verilator-$(VERILATOR_VERSION).tar.gz: mkdir -p $(dir $@) wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@ -rocketchip_csrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/csrc - # Run Verilator to produce a fast binary to emulate this circuit. VERILATOR := $(INSTALLED_VERILATOR) --cc --exe VERILATOR_FLAGS := --top-module $(MODEL) \ - +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ - +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \ - --output-split 20000 \ + +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ + +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \ + --output-split 20000 \ + --output-split-cfuncs 20000 \ -Wno-STMTDLY --x-assign unique \ - -I$(base_dir)/testchipip/vsrc -I$(base_dir)/rocket-chip/vsrc \ - -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(rocketchip_csrc_dir)/verilator.h" + -I$(base_dir)/testchipip/vsrc -I$(base_dir)/rocket-chip/vsrc \ + -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -DTEST_HARNESS=V$(MODEL) -include $(rocketchip_csrc_dir)/verilator.h" diff --git a/vsim/Makefile b/vsim/Makefile index e0383bc..0c017bc 100644 --- a/vsim/Makefile +++ b/vsim/Makefile @@ -1,11 +1,10 @@ base_dir=$(abspath ..) sim_dir=$(abspath .) -PROJECT ?= example -MODEL ?= TestHarness -CONFIG ?= DefaultExampleConfig -CFG_PROJECT ?= $(PROJECT) -TB ?= TestDriver +include $(base_dir)/Makefrag-variables + +sim = $(sim_dir)/simv-$(PROJECT)-$(CONFIG) +sim_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)-debug simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG) simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)-debug @@ -16,17 +15,9 @@ debug: $(simv_debug) include $(base_dir)/Makefrag -rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc - -sim_vsrcs = \ - $(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v \ - $(rocketchip_vsrc_dir)/TestDriver.v \ - $(rocketchip_vsrc_dir)/AsyncResetReg.v \ - $(rocketchip_vsrc_dir)/plusarg_reader.v \ - $(testchip_vsrcs) - -sim_csrcs = \ - $(testchip_csrcs) +ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),) +-include $(build_dir)/$(long_name).d +endif VCS = vcs -full64 @@ -38,7 +29,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1 -CC "-Wl,-rpath,$(RISCV)/lib" \ $(RISCV)/lib/libfesvr.so \ -sverilog \ - +incdir+$(generated_dir) \ + +incdir+$(build_dir) \ +define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \ +define+PRINTF_COND=$(TB).printf_cond \ +define+STOP_COND=!$(TB).reset \ @@ -48,6 +39,9 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1 +define+RANDOMIZE_INVALID_ASSIGN \ +libext+.v \ +VCS_OPTS += +vpi +VCS_OPTS += -CC "-DVCS_VPI" + verilog: $(sim_vsrcs) $(simv): $(sim_vsrcs) $(sim_csrcs) @@ -58,22 +52,10 @@ $(simv_debug) : $(sim_vsrcs) $(sim_csrcs) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ +define+DEBUG -debug_pp -$(output_dir)/%.out: $(output_dir)/% $(simv) - $(simv) +verbose +max-cycles=1000000 $< 3>&1 1>&2 2>&3 | spike-dasm > $@ - -$(output_dir)/%.run: $(output_dir)/% $(simv) - $(simv) +max-cycles=1000000 $< && touch $@ - -$(output_dir)/%.vpd: $(output_dir)/% $(simv_debug) - $(simv_debug) +vcdplusfile=$@ +max-cycles=1000000 $< - -run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests))) - -run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests))) - -run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests))) +exec_sim=$(sim) +permissive -q +ntb_random_seed_automatic +exec_sim_debug=$(sim_debug) +permissive -q +ntb_random_seed_automatic clean: - rm -rf generated-src csrc simv-* ucli.key vc_hdrs.h + rm -rf $(build_dir) csrc simv-* ucli.key vc_hdrs.h -.PHONY: clean +.PHONY: clean default debug