diff --git a/Makefrag b/Makefrag
index 4a6be9f..62f6efc 100644
--- a/Makefrag
+++ b/Makefrag
@@ -25,7 +25,7 @@ include $(testchip_dir)/Makefrag
 CHISEL_ARGS ?=
 
 FIRRTL_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir
-ANNO_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).anno
+ANNO_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).anno.json
 VERILOG_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v
 
 $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(bootrom_img) $(FIRRTL_JAR)
diff --git a/src/main/scala/example/TestHarness.scala b/src/main/scala/example/TestHarness.scala
index e67a189..20b7dc0 100644
--- a/src/main/scala/example/TestHarness.scala
+++ b/src/main/scala/example/TestHarness.scala
@@ -3,7 +3,7 @@ package example
 import chisel3._
 import freechips.rocketchip.diplomacy.LazyModule
 import freechips.rocketchip.config.{Field, Parameters}
-import testchipip.GeneratorApp
+import freechips.rocketchip.util.GeneratorApp
 
 case object BuildTop extends Field[(Clock, Bool, Parameters) => ExampleTopModule[ExampleTop]]
 
@@ -21,6 +21,7 @@ class TestHarness(implicit val p: Parameters) extends Module {
 }
 
 object Generator extends GeneratorApp {
+  val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
   generateFirrtl
   generateAnno
 }
diff --git a/testchipip b/testchipip
index 5aebd3a..208daac 160000
--- a/testchipip
+++ b/testchipip
@@ -1 +1 @@
-Subproject commit 5aebd3a48d029c2b6fa9d2809f35fa21a14d7311
+Subproject commit 208daac5bd0ea3f85c3f1a0925dec3fafb129451